Projekte pro Jahr
Abstract
components and execute software on one or more microcontroller
units (MCU). These MCUs usually contain a fixed integrated
circuit, thus disallowing modifications to their logic at runtime.
While this keeps the instruction set architecture (ISA) fixed as
well, it leaves the software as the only flexible part in the system.
But what if the MCU logic could be easily changed at runtime
in order to fix bugs or if the ISA could be extended on-the-fly in
order to introduce application-specific instructions and features
on demand?
This work demonstrates a concept for introducing more hardware
flexibility through application-specific MCU modifications.
Therefore, the MCU is implemented as a soft core on a fieldprogrammable
gate array (FPGA) and we reconfigure its logic
with support of the operating system (OS) running on it. The
reconfiguration happens on-the-fly, so no interruption of the
application code or even a system restart is required. Therefore,
(i) the MCU pipeline is specially designed for extensibility by new
instructions, and (ii) the FPGA is selected to support partial selfreconfiguration
of its logic cells at runtime. As long as an instruction
is not yet part of the ISA, the OS supports its emulation to
provide a consistent interface for applications. Apart, no special
compiler support is required, but the application must provide
either the emulation code or a hardware description for adding
the required logic. For a proof of concept, we use a RISC-V based
MCU on a Xilinx Artix-7 FPGA and for evaluating the general
benefit of our approach we use an algorithm that is costly when
executed with the original ISA but fast with application-specific
instructions added at runtime. The experimental evaluation also
shows that the on-the-fly hardware update does not disrupt or
compromise the software execution flow.
Titel in Übersetzung | A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime |
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Originalsprache | englisch |
Titel | 24th Euromicro Conference on Digital System Design (DSD) |
Erscheinungsort | Palermo, Italy |
Herausgeber (Verlag) | EUROMICRO |
Seiten | 199 |
Seitenumfang | 9 |
ISBN (elektronisch) | 978-1-6654-2703-6 |
ISBN (Print) | 978-1-6654-2704-3 |
DOIs | |
Publikationsstatus | Veröffentlicht - 1 Sept. 2021 |
Veranstaltung | 2021 Euromicro Conference on Digital System Design : DSD 2021 - Virtuell, Österreich Dauer: 1 Sept. 2021 → 3 Sept. 2021 https://dsd-seaa2021.unipv.it/index.html#page-top |
Konferenz
Konferenz | 2021 Euromicro Conference on Digital System Design |
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Kurztitel | DSD 2021 |
Land/Gebiet | Österreich |
Ort | Virtuell |
Zeitraum | 1/09/21 → 3/09/21 |
Internetadresse |
Fields of Expertise
- Information, Communication & Computing
Fingerprint
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Embedded Automotive Systems
Baunach, M. C., Batista Ribeiro, L., Martins Gomes, R., Malenko, M., Scheipel, T. P., Saikia, A., Nagarajan, D., Manjunath, V., Kissich, M. & Kanics, K.
1/09/14 → …
Projekt: Arbeitsgebiet
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Betriebssysteme für eingebettete Systeme
Baunach, M. C., Martins Gomes, R., Batista Ribeiro, L., Malenko, M., Mauroner, F. & Scheipel, T. P.
1/09/15 → 31/12/23
Projekt: Forschungsprojekt
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Rekonfigurierbare Prozessorarchitekturen
Baunach, M. C., Martins Gomes, R., Batista Ribeiro, L., Malenko, M., Mauroner, F., Scheipel, T. P. & Saikia, A.
1/09/14 → 31/12/23
Projekt: Forschungsprojekt
Aktivitäten
- 1 Vortrag bei Konferenz oder Fachtagung
-
A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Tobias Peter Scheipel (Redner/in)
3 Sept. 2021Aktivität: Vortrag oder Präsentation › Vortrag bei Konferenz oder Fachtagung › Science to science