A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs

Stefan Erb, Wolfgang Pribyl

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem KonferenzbandBegutachtung

Abstract

We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting meth-
ods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical
modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.
Originalspracheenglisch
TitelDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers
Seiten1-6
ISBN (Print)978-1-61284-208-0
DOIs
PublikationsstatusVeröffentlicht - 2011
VeranstaltungDesign, Automation and Test in Europe Conference and Exhibition: DATE 2015 - Grenoble, Frankreich
Dauer: 10 März 201510 März 2015

Konferenz

KonferenzDesign, Automation and Test in Europe Conference and Exhibition
Land/GebietFrankreich
OrtGrenoble
Zeitraum10/03/1510/03/15

Fields of Expertise

  • Information, Communication & Computing

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