Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl

Severin Holzer-Graf; Thomas Krinninger; Martin Andreas Pernull; Martin Schläffer; Peter Schwabe; David Seywald; Wolfgang Wieser

doi:10.1007/978-3-642-36095-4_10

Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl

Severin Holzer-Graf, Thomas Krinninger, Martin Andreas Pernull, Martin Schläffer, Peter Schwabe, David Seywald, Wolfgang Wieser

Publikation: Beitrag in Buch/Bericht/Konferenzband › Beitrag in einem Konferenzband › Begutachtung

Abstract

In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Grøstl. We present a number of new Grøstl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Grøstl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Grøstl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Grøstl that improve the speed by 55% or the memory requirements by 15%.

Originalsprache	englisch
Titel	Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x
Seiten	145-161
DOIs	https://doi.org/10.1007/978-3-642-36095-4_10
Publikationsstatus	Veröffentlicht - 2013
Veranstaltung	Cryptographers' Track at the RSA Conference 2013: CT-RSA 2013 - San Francisco, USA / Vereinigte Staaten Dauer: 25 Feb. 2013 → 1 März 2013

Publikationsreihe

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band	LNCS 7779
ISSN (Print)	1611-3349

Konferenz

Konferenz	Cryptographers' Track at the RSA Conference 2013
Land/Gebiet	USA / Vereinigte Staaten
Ort	San Francisco
Zeitraum	25/02/13 → 1/03/13

Fields of Expertise

Information, Communication & Computing

Treatment code (Nähere Zuordnung)

Application

Zugriff auf Dokument

10.1007/978-3-642-36095-4_10

paper.pdfEingereichtes Manuskript, 290 KB

FWF -ReSIT - Umsetzung eines sicheren Internets der Dinge
Hutter, M. (Teilnehmer (Co-Investigator)), Wenger, E. (Teilnehmer (Co-Investigator)), Schmidt, J.-M. (Teilnehmer (Co-Investigator)), Mendel, F. (Teilnehmer (Co-Investigator)), Mangard, S. (Teilnehmer (Co-Investigator)) & Posch, R. (Projektleiter (Principal Investigator))
1/07/12 → 31/05/16
Projekt: Forschungsprojekt
FWF - kryptographische Hashfu - Analyse von modernen kryptographischen Hashfunktionen II
Nad, T. (Teilnehmer (Co-Investigator)), Mendel, F. (Teilnehmer (Co-Investigator)), Schläffer, M. (Teilnehmer (Co-Investigator)), Lamberger, M. (Teilnehmer (Co-Investigator)) & Rijmen, V. (Projektleiter (Principal Investigator))
1/02/10 → 31/01/13
Projekt: Forschungsprojekt
EU - ECRYPT II - European network of excellence in cryptology - Phase II
Schmidt, J.-M. (Teilnehmer (Co-Investigator)), Nad, T. (Teilnehmer (Co-Investigator)), Kirschbaum, M. (Teilnehmer (Co-Investigator)), Feldhofer, M. (Teilnehmer (Co-Investigator)), Schläffer, M. (Teilnehmer (Co-Investigator)), Aigner, M. J. (Teilnehmer (Co-Investigator)), Rechberger, C. (Teilnehmer (Co-Investigator)), Lamberger, M. (Teilnehmer (Co-Investigator)), Tillich, S. (Teilnehmer (Co-Investigator)), Medwed, M. (Teilnehmer (Co-Investigator)), Hutter, M. (Teilnehmer (Co-Investigator)), Rijmen, V. (Teilnehmer (Co-Investigator)), Mendel, F. (Teilnehmer (Co-Investigator)) & Posch, R. (Projektleiter (Principal Investigator))
1/08/08 → 31/01/13
Projekt: Forschungsprojekt

Dieses zitieren

Holzer-Graf, S., Krinninger, T., Pernull, M. A., Schläffer, M., Schwabe, P., Seywald, D., & Wieser, W. (2013). Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. in Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x (S. 145-161). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band LNCS 7779). https://doi.org/10.1007/978-3-642-36095-4_10

Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. / Holzer-Graf, Severin; Krinninger, Thomas; Pernull, Martin Andreas et al.
Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. 2013. S. 145-161 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band LNCS 7779).

Publikation: Beitrag in Buch/Bericht/Konferenzband › Beitrag in einem Konferenzband › Begutachtung

Holzer-Graf, S, Krinninger, T, Pernull, MA, Schläffer, M, Schwabe, P, Seywald, D & Wieser, W 2013, Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. in Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Bd. LNCS 7779, S. 145-161, Cryptographers' Track at the RSA Conference 2013, San Francisco, California, USA / Vereinigte Staaten, 25/02/13. https://doi.org/10.1007/978-3-642-36095-4_10

Holzer-Graf S, Krinninger T, Pernull MA, Schläffer M, Schwabe P, Seywald D et al. Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. in Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. 2013. S. 145-161. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-36095-4_10

Holzer-Graf, Severin ; Krinninger, Thomas ; Pernull, Martin Andreas et al. / Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. 2013. S. 145-161 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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title = "Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Gr{\o}stl",

abstract = "In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Gr{\o}stl. We present a number of new Gr{\o}stl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Gr{\o}stl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Gr{\o}stl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Gr{\o}stl that improve the speed by 55% or the memory requirements by 15%.",

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AU - Schläffer, Martin

AU - Schwabe, Peter

AU - Seywald, David

AU - Wieser, Wolfgang

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N2 - In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Grøstl. We present a number of new Grøstl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Grøstl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Grøstl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Grøstl that improve the speed by 55% or the memory requirements by 15%.

AB - In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Grøstl. We present a number of new Grøstl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Grøstl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Grøstl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Grøstl that improve the speed by 55% or the memory requirements by 15%.

U2 - 10.1007/978-3-642-36095-4_10

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T2 - Cryptographers' Track at the RSA Conference 2013

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ER -

Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl

Abstract

Publikationsreihe

Konferenz

Fields of Expertise

Treatment code (Nähere Zuordnung)

Zugriff auf Dokument

Fingerprint

Projekte

FWF -ReSIT - Umsetzung eines sicheren Internets der Dinge

FWF - kryptographische Hashfu - Analyse von modernen kryptographischen Hashfunktionen II

EU - ECRYPT II - European network of excellence in cryptology - Phase II

Dieses zitieren