Simple Dflip-flop Behavioral Model of ESD Immunity for use in the ISO 10605 Standard

Guangyao Shen; V Khilkevich; S Yang; D Pommerenke; H Aichele; D Eichel; C Keller

Simple Dflip-flop Behavioral Model of ESD Immunity for use in the ISO 10605 Standard

Guangyao Shen^*, V Khilkevich, S Yang, D Pommerenke, H Aichele, D Eichel, C Keller

^*Korrespondierende/r Autor/-in für diese Arbeit

Publikation: Beitrag in Buch/Bericht/Konferenzband › Beitrag in einem Konferenzband › Begutachtung

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

Originalsprache	englisch
Titel	2014 IEEE International Symposium on Electromagnetic Compatibility, EMC
Seiten	455-459
Seitenumfang	5
Publikationsstatus	Veröffentlicht - 1 Jan. 2014
Extern publiziert	Ja
Veranstaltung	2014 IEEE International Symposium on Electromagnetic Compatibility: EMC 2014 - Raleigh, USA / Vereinigte Staaten Dauer: 3 Aug. 2014 → 8 Aug. 2014

Konferenz

Konferenz	2014 IEEE International Symposium on Electromagnetic Compatibility
Land/Gebiet	USA / Vereinigte Staaten
Ort	Raleigh
Zeitraum	3/08/14 → 8/08/14

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Shen, G, Khilkevich, V, Yang, S, Pommerenke, D, Aichele, H, Eichel, D & Keller, C 2014, Simple Dflip-flop Behavioral Model of ESD Immunity for use in the ISO 10605 Standard. in 2014 IEEE International Symposium on Electromagnetic Compatibility, EMC. S. 455-459, 2014 IEEE International Symposium on Electromagnetic Compatibility, Raleigh, USA / Vereinigte Staaten, 3/08/14.

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AU - Shen, Guangyao

AU - Khilkevich, V

AU - Yang, S

AU - Pommerenke, D

AU - Aichele, H

AU - Eichel, D

AU - Keller, C

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AB - As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

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BT - 2014 IEEE International Symposium on Electromagnetic Compatibility, EMC

T2 - 2014 IEEE International Symposium on Electromagnetic Compatibility

Y2 - 3 August 2014 through 8 August 2014

ER -

Simple Dflip-flop Behavioral Model of ESD Immunity for use in the ISO 10605 Standard

Abstract

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