High-frequency fast frequency-hopping systems require frequency synthesizers to provide multi-gigahertz clocks with a band switching time on the order of few tens of nanoseconds, posing difficult challenges with respect to noise, sidebands, and power dissipation. Conventional phase-locked loop (PLL)-based synthesizers are simply ill-suited due to the long settling times, which are typically tens of microseconds. Recent research has pushed the development of digital-based low-noise high-frequency synthesizers where the traditional analog forward path is replaced by a digital processing core and the VCO is replaced by a Digitally Controlled Oscillator (DCO). The advantages of such architectures include: friendly implementation in newest digital CMOS technologies, improved testability, robustness against PVT variations, low sensitivity to external noise sources, enhanced programmability. Since the frequency control information is stored in digital form in the loop and the DCO can be switched within few nanoseconds from one frequency to another. There are quite a number of aspects which have to be deeply investigated in a feasibility study. These include: 1. Digital phase detector topologies 2. Digital loop filter topologies 3. DCO architectures 4. Phase noise performance 5. Limit cycles and spurs in the spectrum due to the quantization of the phase information 6. How to assure a virtually zero locking time when switching bands 7. Number of supportable bands 8. Area and power consumption estimation At the moment there are no publications or public documents available which report the implementation of fast frequency-hopping systems with a digital synthesizer. Goal of this Laboratory Module is to investigate in depth the feasibility of a digital approach to the frequency synthesis of fast frequency-hopping systems.
|Effective start/end date||1/10/06 → 30/09/09|
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