FATE - Fault-driven Analysis and Testing for Design Robustness and Stability

The main objective of FATE is to provide a human-centred verification approach for cyber-physical systems that will reduce testing effort while increasing coverage. To achieve this goal, the project will leverage recent advances in machine learning, formal methods and technology experience to develop effective and user-friendly methods to reason about correctness and robustness of complex systems during different phases of their development. The project results will contribute to the safety and robustness of cyber-physical applications and will significantly reduce the field returns in the semiconductor industry to faulty chips delivered to customers, while increasing the competitivity of the Austrian semiconductor industry in the light of the EU Chip Act vision.