OpenES - Modeling and Co-simulation for Virtual Prototyping based on Architecture Models

Project: Research project

Project Details


Development of approaches for functional verification of high level use case descriptions, their corresponding SystemC TLM test-benches, and (co)-simulation with architecture or implementation models based on TLM co-simulation. (in Arbeit) In order to improve European electronics system design productivity (faster time-to-market), design quality (less design errors and less re-designs) to stay competitive, the OpenES consortium joins forces to provide missing links in system-level design and to develop common open solutions based on four pillars: - Fill gaps in design flows with new interoperable tools and/or improve existing tools/flows ensuring the semantic continuity of the design flow. - Specifically focus on integral support of both functional and extra-functional requirements from specification to verification, jointly with the use cases defined at system level. - Raise reuse capabilities from IP to HW/SW subsystem in order to eliminate integration effort by supporting reuse of pre-integrated and pre-verified subsystems. - Enhance interoperability of models and tools by upgrading and extending existing young open standards (SystemC TLM, SystemC-AMS, IP-XACT) To demonstrate the efficiency of this approach a new tool in cooperation with CISC Semiconductors is developed in this project. The aim of the tool SHARC is to design, simulate and verify safety-critical systems in the automotive area. Safety turns out to be the key issue for future vehicle development, as the complexity in the automotive area is steadily growing. Especially when systems interact with and have an effect on the physical world, so called cyber-physical systems, its not longer sufficient to test a single behavior. The whole system must be validated as early as possible in the development cycle and at any level of granularity. This is also recommended by the ISO 262626 standard for automotive E/E systems.
Effective start/end date1/01/1431/07/16


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