A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime

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Embedded systems are built from various hardware
components and execute software on one or more microcontroller
units (MCU). These MCUs usually contain a fixed integrated
circuit, thus disallowing modifications to their logic at runtime.
While this keeps the instruction set architecture (ISA) fixed as
well, it leaves the software as the only flexible part in the system.
But what if the MCU logic could be easily changed at runtime
in order to fix bugs or if the ISA could be extended on-the-fly in
order to introduce application-specific instructions and features
on demand?
This work demonstrates a concept for introducing more hardware
flexibility through application-specific MCU modifications.
Therefore, the MCU is implemented as a soft core on a fieldprogrammable
gate array (FPGA) and we reconfigure its logic
with support of the operating system (OS) running on it. The
reconfiguration happens on-the-fly, so no interruption of the
application code or even a system restart is required. Therefore,
(i) the MCU pipeline is specially designed for extensibility by new
instructions, and (ii) the FPGA is selected to support partial selfreconfiguration
of its logic cells at runtime. As long as an instruction
is not yet part of the ISA, the OS supports its emulation to
provide a consistent interface for applications. Apart, no special
compiler support is required, but the application must provide
either the emulation code or a hardware description for adding
the required logic. For a proof of concept, we use a RISC-V based
MCU on a Xilinx Artix-7 FPGA and for evaluating the general
benefit of our approach we use an algorithm that is costly when
executed with the original ISA but fast with application-specific
instructions added at runtime. The experimental evaluation also
shows that the on-the-fly hardware update does not disrupt or
compromise the software execution flow.
Translated title of the contributionA Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Original languageEnglish
Title of host publication24th Euromicro Conference on Digital System Design (DSD)
Place of PublicationPalermo, Italy
Number of pages9
ISBN (Electronic)978-1-6654-2703-6
ISBN (Print)978-1-6654-2704-3
Publication statusPublished - 1 Sept 2021
Event24th Euromicro Conference on Digital System Design: DSD 2021 - Virtuell, Austria
Duration: 1 Sept 20213 Sept 2021


Conference24th Euromicro Conference on Digital System Design
Abbreviated titleDSD 2021
Internet address

Fields of Expertise

  • Information, Communication & Computing

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