A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs

Stefan Erb, Wolfgang Pribyl

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review

Abstract

We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting meth-
ods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical
modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.
Original languageEnglish
Title of host publicationDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2011
PublisherInstitute of Electrical and Electronics Engineers
Pages1-6
ISBN (Print)978-1-61284-208-0
DOIs
Publication statusPublished - 2011
EventDesign, Automation and Test in Europe Conference and Exhibition: DATE 2015 - Grenoble, France
Duration: 10 Mar 201510 Mar 2015

Conference

ConferenceDesign, Automation and Test in Europe Conference and Exhibition
Country/TerritoryFrance
CityGrenoble
Period10/03/1510/03/15

Fields of Expertise

  • Information, Communication & Computing

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