A novel method for ESD soft error analysis on integrated circuits using a TEM cell

Jongsung Lee*, Jaedeok Lim, Byongsu Seol, Zhen Li, David Pommerenke

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


The ultimate goal of this work is to predict ESD system level behavior. A methodology which can evaluate the IC immunity in terms of ESD-induced soft error is introduced. A modified TEM cell and a simple test board with a memory IC are designed for this purpose. The correlation between product level ESD standard test and the proposed IC immunity test is discussed.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, EOS/ESD 2012
Publication statusPublished - 27 Nov 2012
Externally publishedYes
Event34th Annual Electrical Overstress/Electrostatic Discharge Symposium: EOS/ESD 2012 - Tucson, United States
Duration: 9 Sept 201214 Sept 2012

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159


Conference34th Annual Electrical Overstress/Electrostatic Discharge Symposium
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this