Abstract
This paper presents a temperature analysis for NFC-powered Lab-on-Chip (LoC) solutions. It is based on a monolithically implemented LoC and uses a 130 nm standard CMOS process. The LoC has an active chip area of 6.24 mm 2 . An application-independent temperature gathering mesh is implemented on the chip substrate. It allows a real time NFC-caused temperature analysis. Measurement data regarding heat spreading, the influence of the glob top, and the effect of the PCB layout is presented. A warming reduction from 23.05°C to 3.8°C using the same power source is achieved. Detailed data on the temperature gradient over time for warming and cooling is also provided.
Original language | English |
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Title of host publication | 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1058-1061 |
Number of pages | 4 |
Volume | 2018-August |
ISBN (Electronic) | 9781538673928 |
DOIs | |
Publication status | Published - 22 Jan 2019 |
Event | 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada Duration: 5 Aug 2018 → 8 Aug 2018 |
Conference
Conference | 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 |
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Country/Territory | Canada |
City | Windsor |
Period | 5/08/18 → 8/08/18 |
Keywords
- 130 nm
- CMOS
- Lab-on-chip
- NFC
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering