Abstract
Optimizing electrostatic discharge (ESD) protection strategies requires simulation models of both on- and off-die ESD devices, but detailed information about on-die ESD protection is rarely available. Methods are proposed in the following paper to characterize and model the on-chip ESD protection using only measurements, with minimal a priori information about how the protection is implemented. The characterization targets a three-terminal (rather than the traditional two-terminal) protection structure, including the I/O, Vdd, Vss pins, and allows for current to flow between multiple pins simultaneously. A previously-developed behavioral model for TVS devices is used to capture the ESD behavior of the integrated circuit (IC), including its linear, quasi-static, and transient nonlinear response. The approach is used to model the equivalent current that flows through the on-chip ESD protection of two commercial ICs. The model of the on-chip ESD protection is combined with a behavioral model of an off-chip transient voltage suppressor to demonstrate their combined performance in a system-efficient ESD design (SEED) simulation. The model is validated both when the IC is powered-off and powered-on. The SEED model was able to predict quasistatic and peak voltages and currents at the IC with less than a 10% error.
Original language | English |
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Pages (from-to) | 1802-1811 |
Number of pages | 10 |
Journal | IEEE Transactions on Electromagnetic Compatibility |
Volume | 64 |
Issue number | 6 |
DOIs | |
Publication status | Published - 1 Dec 2022 |
Keywords
- Electrostatic discharge
- experimental characteri- zation
- integrated circuit
- modeling
- system-level ESD
ASJC Scopus subject areas
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Electrical and Electronic Engineering