Compact Hardware Implemenations of the SHA-3 Candidates ARIRANG, BLAKE, Grøstl, and Skein

Stefan Tillich, Martin Feldhofer, Wolfgang Issovits, Thomas Kern, Hermann Kureck, Michael Mühlberghuber, Georg Neubauer, Andreas Reiter, Armin Köfler, Mathias Mayrhofer

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

The weakening of the widely used SHA-1 hash function has also cast doubts on the strength of the related algorithms of the SHA-2 family. The US NIST has therefore initiated the SHA-3 competition in order to select a modern hash function algorithm as a “backup” for SHA-2.
This algorithm should be efficiently implementable both in software and hardware under different constraints. In this paper, we present hardware implementations of the
four SHA-3 candidates ARIRANG, BLAKE, Grøstl, and Skein with the primary constraint of minimizing chip area.
Original languageEnglish
Title of host publicationTagungsband Austrochip 2009, 7. Oktober 2009
Place of PublicationGraz
Pages69-74
Publication statusPublished - 2009
EventAustrochip 2009 - Graz, Austria
Duration: 7 Oct 2009 → 7 Oct 2009

Conference

ConferenceAustrochip 2009
Country/TerritoryAustria
CityGraz
Period7/10/09 → 7/10/09

Treatment code (Nähere Zuordnung)

  • Application
  • Experimental

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