Design and Performance Considerations for an On-Chip Jitter Analysis System

Stefan Erb; Wolfgang Pribyl

doi:10.1109/ISCAS.2010.5537662

Design and Performance Considerations for an On-Chip Jitter Analysis System

Stefan Erb, Wolfgang Pribyl

Institute of Electronics (4390)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Original language	English
Title of host publication	Proceedings of 2010 IEEE International Symposium on Circuits and Systems
Publisher	.
Pages	3969-3972
DOIs	https://doi.org/10.1109/ISCAS.2010.5537662
Publication status	Published - 2010
Event	IEEE International Symposium on Circuits and Systems: ISCAS 2010 - Paris, France Duration: 30 May 2010 → 2 Jun 2010

Conference

Conference	IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS
Country/Territory	France
City	Paris
Period	30/05/10 → 2/06/10

Treatment code (Nähere Zuordnung)

Application
Theoretical

Access to Document

10.1109/ISCAS.2010.5537662

Cite this

@inproceedings{6ebbf4bcd77640798ce4175c910d4c16,

title = "Design and Performance Considerations for an On-Chip Jitter Analysis System",

author = "Stefan Erb and Wolfgang Pribyl",

year = "2010",

doi = "10.1109/ISCAS.2010.5537662",

language = "English",

pages = "3969--3972",

booktitle = "Proceedings of 2010 IEEE International Symposium on Circuits and Systems",

publisher = ".",

note = "IEEE International Symposium on Circuits and Systems : ISCAS 2010, ISCAS ; Conference date: 30-05-2010 Through 02-06-2010",

}

TY - GEN

T1 - Design and Performance Considerations for an On-Chip Jitter Analysis System

AU - Erb, Stefan

AU - Pribyl, Wolfgang

PY - 2010

Y1 - 2010

UR - http://www.ieeexplore.ieee.org

U2 - 10.1109/ISCAS.2010.5537662

DO - 10.1109/ISCAS.2010.5537662

M3 - Conference paper

SP - 3969

EP - 3972

BT - Proceedings of 2010 IEEE International Symposium on Circuits and Systems

PB - .

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 30 May 2010 through 2 June 2010

ER -

Design and Performance Considerations for an On-Chip Jitter Analysis System

Conference

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JUDY-Integrated Jitter Measurement: A Concept Study for High-Speed Clock Systems

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Design and Performance Considerations for an On-Chip Jitter Analysis System

Conference

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Projects

JUDY-Integrated Jitter Measurement: A Concept Study for High-Speed Clock Systems

Cite this