Abstract
This thesis describes a development flow for a Switched-Capacitor DC-DC converter creating a negative voltage. This includes conceptual considerations, such as topology and approximate performance calculations, as well as the design of the circuit in Bipolar-CMOS-DMOS (BCD) technology and the verification of the design in comparison to the conceptual approximations.
The use of triple-well NMOS and DeMOS devices is reviewed. Additionally, needed circuits such as level shifters and voltage buffers are explained. Furthermore, an approach for area optimisation of the used switch transistors is presented. Other considerations such as external devices and the introduced parasitics and their effects are also modelled and discussed.
The use of triple-well NMOS and DeMOS devices is reviewed. Additionally, needed circuits such as level shifters and voltage buffers are explained. Furthermore, an approach for area optimisation of the used switch transistors is presented. Other considerations such as external devices and the introduced parasitics and their effects are also modelled and discussed.
Original language | English |
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Qualification | Master of Science |
Awarding Institution |
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Supervisors/Advisors |
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Award date | 26 Apr 2018 |
Publication status | Published - 26 Apr 2018 |