Effective Dynamic Scheduling on Heterogeneous Multi/Manycore Desktop Platforms

A. Binotto; B. Pedras; M. Götz; Arjan Kuijper; C. E. Pereira; Wolf-Dietrich Fellner

doi:10.1109/SBAC-PADW.2010.6

Effective Dynamic Scheduling on Heterogeneous Multi/Manycore Desktop Platforms

A. Binotto, B. Pedras, M. Götz, Arjan Kuijper, C. E. Pereira, Wolf-Dietrich Fellner

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Original language	English
Title of host publication	International Symposium on Computer Architecture and High Performance Computing
Publisher	Institute of Electrical and Electronics Engineers
Pages	37-42
ISBN (Print)	978-0-7695-4276-8
DOIs	https://doi.org/10.1109/SBAC-PADW.2010.6
Publication status	Published - 2010
Event	International Symposium on Computer Architecture and High Performance Computing - Petropolis, Brazil Duration: 27 Oct 2010 → 30 Oct 2010

Conference

Conference	International Symposium on Computer Architecture and High Performance Computing
Country/Territory	Brazil
City	Petropolis
Period	27/10/10 → 30/10/10

Treatment code (Nähere Zuordnung)

Application

Access to Document

10.1109/SBAC-PADW.2010.6

Cite this

Binotto, A, Pedras, B, Götz, M, Kuijper, A, Pereira, CE & Fellner, W-D 2010, Effective Dynamic Scheduling on Heterogeneous Multi/Manycore Desktop Platforms. in International Symposium on Computer Architecture and High Performance Computing. Institute of Electrical and Electronics Engineers, pp. 37-42, International Symposium on Computer Architecture and High Performance Computing, Petropolis, Brazil, 27/10/10. https://doi.org/10.1109/SBAC-PADW.2010.6

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note = "1st Workshop on Applications for Multi and Many Core Architectures (WAMMCA); International Symposium on Computer Architecture and High Performance Computing ; Conference date: 27-10-2010 Through 30-10-2010",

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AU - Pedras, B.

AU - Götz, M.

AU - Kuijper, Arjan

AU - Pereira, C. E.

AU - Fellner, Wolf-Dietrich

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M3 - Conference paper

SN - 978-0-7695-4276-8

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BT - International Symposium on Computer Architecture and High Performance Computing

PB - Institute of Electrical and Electronics Engineers

T2 - International Symposium on Computer Architecture and High Performance Computing

Y2 - 27 October 2010 through 30 October 2010

ER -