Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl

Severin Holzer-Graf; Thomas Krinninger; Martin Andreas Pernull; Martin Schläffer; Peter Schwabe; David Seywald; Wolfgang Wieser

doi:10.1007/978-3-642-36095-4_10

Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl

Severin Holzer-Graf, Thomas Krinninger, Martin Andreas Pernull, Martin Schläffer, Peter Schwabe, David Seywald, Wolfgang Wieser

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Grøstl. We present a number of new Grøstl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Grøstl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Grøstl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Grøstl that improve the speed by 55% or the memory requirements by 15%.

Original language	English
Title of host publication	Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x
Pages	145-161
DOIs	https://doi.org/10.1007/978-3-642-36095-4_10
Publication status	Published - 2013
Event	Cryptographers' Track at the RSA Conference 2013: CT-RSA 2013 - San Francisco, United States Duration: 25 Feb 2013 → 1 Mar 2013

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	LNCS 7779
ISSN (Print)	1611-3349

Conference

Conference	Cryptographers' Track at the RSA Conference 2013
Country/Territory	United States
City	San Francisco
Period	25/02/13 → 1/03/13

Fields of Expertise

Information, Communication & Computing

Treatment code (Nähere Zuordnung)

Application

Access to Document

10.1007/978-3-642-36095-4_10

paper.pdfSubmitted manuscript, 290 KB

FWF - ReSIT - Realizing a Secure Internet of Things
Hutter, M. (Co-Investigator (CoI)), Wenger, E. (Co-Investigator (CoI)), Schmidt, J.-M. (Co-Investigator (CoI)), Mendel, F. (Co-Investigator (CoI)), Mangard, S. (Co-Investigator (CoI)) & Posch, R. (Principal Investigator (PI))
1/07/12 → 31/05/16
Project: Research project
FWF - kryptographische Hashfu - Cryptanalysis of modern cryptographic hash functions II
Nad, T. (Co-Investigator (CoI)), Mendel, F. (Co-Investigator (CoI)), Schläffer, M. (Co-Investigator (CoI)), Lamberger, M. (Co-Investigator (CoI)) & Rijmen, V. (Principal Investigator (PI))
1/02/10 → 31/01/13
Project: Research project
EU - ECRYPT II - European network of excellence in cryptology - Phase II
Schmidt, J.-M. (Co-Investigator (CoI)), Nad, T. (Co-Investigator (CoI)), Kirschbaum, M. (Co-Investigator (CoI)), Feldhofer, M. (Co-Investigator (CoI)), Schläffer, M. (Co-Investigator (CoI)), Aigner, M. J. (Co-Investigator (CoI)), Rechberger, C. (Co-Investigator (CoI)), Lamberger, M. (Co-Investigator (CoI)), Tillich, S. (Co-Investigator (CoI)), Medwed, M. (Co-Investigator (CoI)), Hutter, M. (Co-Investigator (CoI)), Rijmen, V. (Co-Investigator (CoI)), Mendel, F. (Co-Investigator (CoI)) & Posch, R. (Principal Investigator (PI))
1/08/08 → 31/01/13
Project: Research project

Cite this

Holzer-Graf, S., Krinninger, T., Pernull, M. A., Schläffer, M., Schwabe, P., Seywald, D., & Wieser, W. (2013). Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. In Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x (pp. 145-161). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. LNCS 7779). https://doi.org/10.1007/978-3-642-36095-4_10

Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. / Holzer-Graf, Severin; Krinninger, Thomas; Pernull, Martin Andreas et al.
Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. 2013. p. 145-161 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. LNCS 7779).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Holzer-Graf, S, Krinninger, T, Pernull, MA, Schläffer, M, Schwabe, P, Seywald, D & Wieser, W 2013, Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. in Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. LNCS 7779, pp. 145-161, Cryptographers' Track at the RSA Conference 2013, San Francisco, California, United States, 25/02/13. https://doi.org/10.1007/978-3-642-36095-4_10

Holzer-Graf S, Krinninger T, Pernull MA, Schläffer M, Schwabe P, Seywald D et al. Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. In Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. 2013. p. 145-161. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-36095-4_10

Holzer-Graf, Severin ; Krinninger, Thomas ; Pernull, Martin Andreas et al. / Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl. Cryptographers' Track at the RSA Conference 2013, CT-RSA 2013x^x. 2013. pp. 145-161 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Gr{\o}stl. We present a number of new Gr{\o}stl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Gr{\o}stl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Gr{\o}stl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Gr{\o}stl that improve the speed by 55% or the memory requirements by 15%.",

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AB - In this paper we evaluate and improve different vector implementation techniques of AES-based designs. We analyze how well the T-table, bitsliced and bytesliced implementation techniques apply to the SHA-3 finalist Grøstl. We present a number of new Grøstl implementations that improve upon many previous results. For example, our fastest ARM NEON implementation of Grøstl is 40% faster than the previously fastest ARM implementation. We present the first Intel AVX2 implementations of Grøstl, which require 40% less instructions than previous implementations. Furthermore, we present ARM Cortex-M0 implementations of Grøstl that improve the speed by 55% or the memory requirements by 15%.

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Efficient Vector Implementations of AES-based Designs: A Case Study and New Implementations for Grøstl

Abstract

Publication series

Conference

Fields of Expertise

Treatment code (Nähere Zuordnung)

Access to Document

Fingerprint

Projects

FWF - ReSIT - Realizing a Secure Internet of Things

FWF - kryptographische Hashfu - Cryptanalysis of modern cryptographic hash functions II

EU - ECRYPT II - European network of excellence in cryptology - Phase II

Cite this