ESD immunity prediction of D flip-flop in the ISO 10605 standard using a behavioral modeling methodology

Guangyao Shen; Sen Yang; Victor V. Khilkevich; David J. Pommerenke; Hermann L. Aichele; Dirk R. Eichel; Christoph Keller

doi:10.1109/TEMC.2015.2418715

ESD immunity prediction of D flip-flop in the ISO 10605 standard using a behavioral modeling methodology

Guangyao Shen^*, Sen Yang, Victor V. Khilkevich, David J. Pommerenke, Hermann L. Aichele, Dirk R. Eichel, Christoph Keller

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

Original language	English
Article number	7089237
Pages (from-to)	651-659
Number of pages	9
Journal	IEEE Transactions on Electromagnetic Compatibility
Volume	57
Issue number	4
DOIs	https://doi.org/10.1109/TEMC.2015.2418715
Publication status	Published - 1 Aug 2015
Externally published	Yes

Keywords

Behavioral model
flip-flop
ISO 10605
parallel harness
twisted pair harness

ASJC Scopus subject areas

Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/TEMC.2015.2418715

Cite this

@article{687bf84ff79f4ccebb3b0a9dabcf3303,

title = "ESD immunity prediction of D flip-flop in the ISO 10605 standard using a behavioral modeling methodology",

abstract = "As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.",

keywords = "Behavioral model, flip-flop, ISO 10605, parallel harness, twisted pair harness",

author = "Guangyao Shen and Sen Yang and Khilkevich, {Victor V.} and Pommerenke, {David J.} and Aichele, {Hermann L.} and Eichel, {Dirk R.} and Christoph Keller",

year = "2015",

month = aug,

day = "1",

doi = "10.1109/TEMC.2015.2418715",

language = "English",

volume = "57",

pages = "651--659",

journal = "IEEE Transactions on Electromagnetic Compatibility",

issn = "0018-9375",

publisher = "Institute of Electrical and Electronics Engineers",

number = "4",

}

TY - JOUR

T1 - ESD immunity prediction of D flip-flop in the ISO 10605 standard using a behavioral modeling methodology

AU - Shen, Guangyao

AU - Yang, Sen

AU - Khilkevich, Victor V.

AU - Pommerenke, David J.

AU - Aichele, Hermann L.

AU - Eichel, Dirk R.

AU - Keller, Christoph

PY - 2015/8/1

Y1 - 2015/8/1

N2 - As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

AB - As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

KW - Behavioral model

KW - flip-flop

KW - ISO 10605

KW - parallel harness

KW - twisted pair harness

UR - http://www.scopus.com/inward/record.url?scp=85027934919&partnerID=8YFLogxK

U2 - 10.1109/TEMC.2015.2418715

DO - 10.1109/TEMC.2015.2418715

M3 - Article

AN - SCOPUS:85027934919

SN - 0018-9375

VL - 57

SP - 651

EP - 659

JO - IEEE Transactions on Electromagnetic Compatibility

JF - IEEE Transactions on Electromagnetic Compatibility

IS - 4

M1 - 7089237

ER -

ESD immunity prediction of D flip-flop in the ISO 10605 standard using a behavioral modeling methodology

Abstract

Keywords

ASJC Scopus subject areas

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