Abstract
In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase.
Original language | English |
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Article number | 9203841 |
Pages (from-to) | 375-383 |
Number of pages | 9 |
Journal | IEEE Transactions on Electromagnetic Compatibility |
Volume | 63 |
Issue number | 2 |
DOIs | |
Publication status | Published - Apr 2021 |
Keywords
- Circuit model
- electrostatic discharge (ESD)
- SEED
- soft failure (SF)
- SPICE
- transmission line pulse (TLP)
ASJC Scopus subject areas
- Condensed Matter Physics
- Atomic and Molecular Physics, and Optics
- Electrical and Electronic Engineering