Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system

Sebastian Schmitt, Johann Klahn, Guillaume Bellec, Andreas Grubl, Maurice Guttler, Andreas Hartel, Stephan Hartmann, Dan Husmann, Kai Husmann, Sebastian Jeltsch, Vitali Karasenko, Mitja Kleider, Christoph Koke, Alexander Kononov, Christian Mauch, Eric Muller, Paul Muller, Johannes Partzsch, Mihai A. Petrovici, Stefan SchieferStefan Scholze, Vasilis Thanasoulis, Bernhard Vogginger, Robert Legenstein, Wolfgang Maass, Christian Mayr, Rene Schuffny, Johannes Schemmel, Karlheinz Meier

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


Emulating spiking neural networks on analog neuromorphic hardware offers several advantages over simulating them on conventional computers, particularly in terms of speed and energy consumption. However, this usually comes at the cost of reduced control over the dynamics of the emulated networks. In this paper, we demonstrate how iterative training of a hardware-emulated network can compensate for anomalies induced by the analog substrate. We first convert a deep neural network trained in software to a spiking network on the BrainScaleS wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10000 compared to the biological time domain. This mapping is followed by the in-the-loop training, where in each training step, the network activity is first recorded in hardware and then used to compute the parameter updates in software via backpropagation. An essential finding is that the parameter updates do not have to be precise, but only need to approximately follow the correct gradient, which simplifies the computation of updates. Using this approach, after only several tens of iterations, the spiking network shows an accuracy close to the ideal software-emulated prototype. The presented techniques show that deep spiking networks emulated on analog neuromorphic devices can attain good computational performance despite the inherent variations of the analog substrate.

Original languageEnglish
Title of host publication2017 International Joint Conference on Neural Networks, IJCNN 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers
Number of pages8
ISBN (Electronic)9781509061815
Publication statusPublished - 30 Jun 2017
Event2017 International Joint Conference on Neural Networks: IJCNN 2017 - Anchorage, United States
Duration: 14 May 201719 May 2017

Publication series

NameProceedings of the International Joint Conference on Neural Networks


Conference2017 International Joint Conference on Neural Networks
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Software
  • Artificial Intelligence

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