Due to their basic physical properties, power MOSFETs exhibit an output capacitance C oss that is dependent on the drain-source voltage. This (nonlinear) parasitic capacitance has to be charged at turn-off of the MOSFET by the drain-source current in rectifier applications that yield input current distortions. A detailed analysis shows that the nonlinear behavior of this capacitance is even more pronounced for modern super junction MOSFET devices. Whereas C oss increases with increasing chip area, the on-state resistance of the MOSFET decreases accordingly. Hence, a tradeoff between efficiency and input current distortions exists. A detailed analysis of this effect considering different semiconductor technologies is given in this study and a Pareto curve in the η-THD I space is drawn that clearly highlights this relationship. It is further shown that the distortions can be reduced considerably by the application of a proper feedforward control signal counter- acting the nonlinear switching delay due to C oss . The theoretical considerations are verified by experimental results taken from 10-kW laboratory prototypes with the switching frequencies of 250 kHz and 1 MHz.