Pre-charge optimization in Sidewall Spacer Memory Bit Cell with respect to Total Ionizing Dose

Tommaso Vincenzi*, Gregor Schatzberger, Alicja Malgorzata Michalowska-Forsyth

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper analyses a charge-based Non-Volatile Memory device: the Sidewall Spacer. Multiple test-dies from a 55nm standard CMOS process are tested up to 500krad assessing data retention depending on charge injection in the nitride spacer.
Original languageEnglish
Number of pages5
Publication statusPublished - Nov 2020
Event2020 Nuclear & Space Radiation Effects Conference - Virtuell
Duration: 1 Dec 20208 Dec 2020
http://www.nsrec.com/

Conference

Conference2020 Nuclear & Space Radiation Effects Conference
Abbreviated titleNSREC 2020
CityVirtuell
Period1/12/208/12/20
Internet address

Keywords

  • flash memory
  • Nonvolatile Memories
  • radiation effects
  • Total Ionizing Dose
  • x-ray
  • charge based

Fingerprint

Dive into the research topics of 'Pre-charge optimization in Sidewall Spacer Memory Bit Cell with respect to Total Ionizing Dose'. Together they form a unique fingerprint.

Cite this