Proteus: A Pipelined NTT Architecture Generator

Number theoretic transform (NTT) is a fundamental building block in emerging cryptographic constructions such as fully homomorphic encryption (FHE), post-quantum cryptography (PQC), and zero-knowledge proof (ZKP). In this work, we introduce Proteus, an open-source parametric hardware to generate pipelined architectures for the NTT. For a given parameter set including the polynomial degree and size of the coefficient modulus, Proteus can generate Radix-2 NTT architectures using single-path delay feedback (SDF) and multipath delay commutator (MDC) approaches. We also present a detailed analysis of NTT implementation approaches and use several optimizations to achieve the best NTT configuration. Our evaluations demonstrate performance gain up to 1.8 × compared to SDF and MDC-based NTT implementations in the literature. Our SDF and MDC architectures use 1.75 × and 6.5 × less DSPs, and 3 × and 10.5 × less BRAMs, respectively, compared to state-of-the-art SDF and MDC-based NTT implementations.