Abstract
As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.
Original language | English |
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Title of host publication | 2014 IEEE International Symposium on Electromagnetic Compatibility, EMC |
Pages | 455-459 |
Number of pages | 5 |
Publication status | Published - 1 Jan 2014 |
Externally published | Yes |
Event | 2014 IEEE International Symposium on Electromagnetic Compatibility: EMC 2014 - Raleigh, United States Duration: 3 Aug 2014 → 8 Aug 2014 |
Conference
Conference | 2014 IEEE International Symposium on Electromagnetic Compatibility |
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Country/Territory | United States |
City | Raleigh |
Period | 3/08/14 → 8/08/14 |