Simple Dflip-flop Behavioral Model of ESD Immunity for use in the ISO 10605 Standard

Guangyao Shen*, V Khilkevich, S Yang, D Pommerenke, H Aichele, D Eichel, C Keller

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.
Original languageEnglish
Title of host publication2014 IEEE International Symposium on Electromagnetic Compatibility, EMC
Pages455-459
Number of pages5
Publication statusPublished - 1 Jan 2014
Externally publishedYes
Event2014 IEEE International Symposium on Electromagnetic Compatibility: EMC 2014 - Raleigh, United States
Duration: 3 Aug 20148 Aug 2014

Conference

Conference2014 IEEE International Symposium on Electromagnetic Compatibility
Country/TerritoryUnited States
CityRaleigh
Period3/08/148/08/14

Fingerprint

Dive into the research topics of 'Simple Dflip-flop Behavioral Model of ESD Immunity for use in the ISO 10605 Standard'. Together they form a unique fingerprint.

Cite this