Stitching FPGA Fabrics with FABulous and OpenLane 2

This paper presents an open-source approach to automatically stitch FPGA fabrics generated by FABulous. We use the Python API provided by OpenLane 2 to programmatically place pins and macros. The tiles of the fabric are arranged and stitched together depending on their size and the geometry of the FPGA. Thus, much faster design iterations can be achieved for various homogeneous FPGA fabrics. We compare fabric stitching with a simple, non-hierarchical approach, so-called sea of gates, in terms of time required for the physical implementation, maximum RAM usage and area demand. Our findings show that the sea of gates approach yields the best results in terms of area, but also requires significant runtime for large fabrics. For an FPGA with the size of 10×10 Configurable Logic Blocks, fabric stitching takes 12 times less runtime and consumes only 21% of the maximum RAM compared to the sea of gates approach for the same target density of 50%, as the tiles only need to be hardened once and are then stitched together. Fabric stitching with higher-density tiles (70%) reduces the area overhead to -4.17%, meaning less area demand than the sea of gates approach for just a small runtime increase. The physical implementation is performed using the open-source SKY130 PDK.