Systematic Analysis of Randomization-based Protected Cache Architectures

Antoon Purnal, Lukas Giner, Daniel Gruß, Ingrid Verbauwhede

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


Recent secure cache designs aim to mitigate side-channel attacks by randomizing the mapping from memory addresses to cache sets.
As vendors investigate deployment of these caches, it is crucial to understand their actual security.

In this paper, we consolidate existing randomization-based secure caches into a generic cache model.
We then comprehensively analyze the security of existing designs, including CEASER-S and SCATTERCACHE, by mapping them to instances of this model.
We tailor cache attacks for randomized caches using a novel PRIME+PRUNE+PROBE technique, and optimize it using burst accesses, bootstrapping, and multi-step profiling.
PRIME+PRUNE+PROBE constructs probabilistic but reliable eviction sets, enabling attacks previously assumed to be computationally infeasible.
We also simulate an end-to-end attack, leaking secrets from a vulnerable AES implementation.
Finally, a case study of CEASER-S reveals that cryptographic weaknesses in the randomization algorithm can lead to a complete security subversion.

Our systematic analysis yields more realistic and comparable security levels for randomized caches.
As we quantify how design parameters influence the security level, our work leads to important conclusions for future work on secure cache designs.
Original languageEnglish
Title of host publication2021 IEEE Symposium on Security and Privacy (SP)
ISBN (Electronic)978-1-7281-8934-5
Publication statusPublished - Aug 2021
Event42th IEEE Symposium on Security and Privacy - San Francisco, Virtuell, United States
Duration: 20 May 202121 May 2021


Conference42th IEEE Symposium on Security and Privacy
Abbreviated titleIEEE SP 2021
Country/TerritoryUnited States


  • secure cache
  • cache architecture
  • side channel


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