The PCB level ESD immunity study by using 3 dimension ESD scan system

Kai Wang; David Johannes Pommerenke; Jian Min  Zhang; Ramachandran Chundru

doi:10.1109/ISEMC.2004.1349812

The PCB level ESD immunity study by using 3 dimension ESD scan system

Kai Wang, David Johannes Pommerenke, Jian Min Zhang, Ramachandran Chundru

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.

Original language	English
Title of host publication	Electromagnetic Compatibility 2004
Pages	343 - 348
Volume	2
DOIs	https://doi.org/10.1109/ISEMC.2004.1349812
Publication status	Published - 2004
Externally published	Yes
Event	2004 IEEE International Symposium on Electromagnetic Compatibility: EMC 2004 - Santa Clara, United States Duration: 9 Aug 2004 → 13 Aug 2004

Conference

Conference	2004 IEEE International Symposium on Electromagnetic Compatibility
Country/Territory	United States
City	Santa Clara
Period	9/08/04 → 13/08/04

Access to Document

10.1109/ISEMC.2004.1349812

Cite this

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title = "The PCB level ESD immunity study by using 3 dimension ESD scan system",

abstract = "The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.",

author = "Kai Wang and Pommerenke, {David Johannes} and Zhang, {Jian Min} and Ramachandran Chundru",

year = "2004",

doi = "10.1109/ISEMC.2004.1349812",

language = "English",

isbn = "0-7803-8443-1",

volume = "2",

pages = "343 -- 348 ",

booktitle = "Electromagnetic Compatibility 2004",

note = "2004 IEEE International Symposium on Electromagnetic Compatibility : EMC 2004 ; Conference date: 09-08-2004 Through 13-08-2004",

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AU - Wang, Kai

AU - Pommerenke, David Johannes

AU - Zhang, Jian Min

AU - Chundru, Ramachandran

PY - 2004

Y1 - 2004

N2 - The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.

AB - The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.

U2 - 10.1109/ISEMC.2004.1349812

DO - 10.1109/ISEMC.2004.1349812

M3 - Conference paper

SN - 0-7803-8443-1

VL - 2

SP - 343

EP - 348

BT - Electromagnetic Compatibility 2004

T2 - 2004 IEEE International Symposium on Electromagnetic Compatibility

Y2 - 9 August 2004 through 13 August 2004

ER -