The PCB level ESD immunity study by using 3 dimension ESD scan system

Kai Wang, David Johannes Pommerenke, Jian Min Zhang, Ramachandran Chundru

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.
Original languageEnglish
Title of host publicationElectromagnetic Compatibility 2004
Pages343 - 348
Publication statusPublished - 2004
Externally publishedYes
Event2004 IEEE International Symposium on Electromagnetic Compatibility: EMC 2004 - Santa Clara, United States
Duration: 9 Aug 200413 Aug 2004


Conference2004 IEEE International Symposium on Electromagnetic Compatibility
Country/TerritoryUnited States
CitySanta Clara

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