VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors

Stefan Tillich; Johann Großschädl

doi:10.1007/978-3-540-73074-3_5

VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors

Stefan Tillich, Johann Großschädl

Institute of Applied Information Processing and Communications (7050)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

Embedded systems require efficient yet flexible implementations of cryptographic primitives with a minimal impact on the overall cost of a device. In this paper we present the design of a functional unit (FU) for accelerating the execution of cryptographic software on 32-bit processors. The FU is basically a multiply-accumulate (MAC) unit able to perform multiplications and MAC operations on integers and binary polynomials. Polynomial arithmetic is a performance-critical building block of numerous cryptosystems using binary extension fields, including public-key primitives based on elliptic curves (e.g. ECDSA), symmetric ciphers (e.g. AES or Twofish), and hash functions (e.g. Whirlpool). We integrated the FU into the Leon2 SPARC V8 core and prototyped the extended processor in an FPGA. All operations provided by the FU are accessible to the programmer through custom instructions. Our results show that the FU allows to accelerate the execution of 128-bit AES by up to 78% compared to a conventional software implementation using only native SPARC V8 instructions. Moreover, the custom instructions reduce the code size by up to 87.4%. The FU increases the silicon area of the Leon2 core by just 8,352 gates and has almost no impact on its cycle time.

Original language	English
Title of host publication	Arithmetic of Finite Fields
Subtitle of host publication	First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings
Editors	Claude Carlet
Place of Publication	Berlin; Heidelberg
Publisher	Springer Verlag
Pages	40-54
ISBN (Print)	978-3-540-73073-6
DOIs	https://doi.org/10.1007/978-3-540-73074-3_5
Publication status	Published - 2007
Event	International Workshop on the Arithmetic of Finite Fields - Madrid, Spain Duration: 21 Jun 2007 → 22 Jun 2007

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer Verlag
Volume	4547

Conference

Conference	International Workshop on the Arithmetic of Finite Fields
Country/Territory	Spain
City	Madrid
Period	21/06/07 → 22/06/07

Treatment code (Nähere Zuordnung)

Application
Experimental

Access to Document

10.1007/978-3-540-73074-3_5

WAIFI2007_VIFFinal published version, 257 KB

EU - SMEPP - Secure Middleware for embedded Peer-to-Peer Systems
Tillich, S. (Co-Investigator (CoI)), Wolkerstorfer, J. (Co-Investigator (CoI)), Payer, U. (Co-Investigator (CoI)), Kraxberger, S. (Co-Investigator (CoI)), Aigner, M. J. (Principal Investigator (PI)) & Posch, R. (Co-Investigator (CoI))
1/09/06 → 31/08/09
Project: Research project
Instruction Set Extensions and Architectural Enhancements for Public-Key Cryptography on General-Purpose RISC Processors
Tillich, S., Großschädl, J., Szekely, A. & Posch, K.
1/12/03 → 31/10/06
Project: Research project
VLSI Design
Medwed, M. (Co-Investigator (CoI)), Wenger, E. (Co-Investigator (CoI)), Aigner, M. J. (Co-Investigator (CoI)), Posch, K.-C. (Co-Investigator (CoI)), Hutter, M. (Co-Investigator (CoI)), Kirschbaum, M. (Co-Investigator (CoI)), Schmidt, J.-M. (Co-Investigator (CoI)), Posch, R. (Co-Investigator (CoI)), Dominikus, S. (Co-Investigator (CoI)), Szekely, A. (Co-Investigator (CoI)), Feldhofer, M. (Co-Investigator (CoI)) & Plos, T. (Co-Investigator (CoI))
1/01/95 → 15/07/19
Project: Research area

Cite this

Tillich, S., & Großschädl, J. (2007). VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors. In C. Carlet (Ed.), Arithmetic of Finite Fields: First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings (pp. 40-54). (Lecture Notes in Computer Science; Vol. 4547). Springer Verlag. https://doi.org/10.1007/978-3-540-73074-3_5

VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors. / Tillich, Stefan; Großschädl, Johann.
Arithmetic of Finite Fields: First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings. ed. / Claude Carlet. Berlin; Heidelberg: Springer Verlag, 2007. p. 40-54 (Lecture Notes in Computer Science; Vol. 4547).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Tillich, S & Großschädl, J 2007, VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors. in C Carlet (ed.), Arithmetic of Finite Fields: First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings. Lecture Notes in Computer Science, vol. 4547, Springer Verlag, Berlin; Heidelberg, pp. 40-54, International Workshop on the Arithmetic of Finite Fields, Madrid, Spain, 21/06/07. https://doi.org/10.1007/978-3-540-73074-3_5

Tillich S, Großschädl J. VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors. In Carlet C, editor, Arithmetic of Finite Fields: First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings. Berlin; Heidelberg: Springer Verlag. 2007. p. 40-54. (Lecture Notes in Computer Science). doi: 10.1007/978-3-540-73074-3_5

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VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-bit Processors

Abstract

Publication series

Conference

Treatment code (Nähere Zuordnung)

Access to Document

Fingerprint

Projects

EU - SMEPP - Secure Middleware for embedded Peer-to-Peer Systems

Instruction Set Extensions and Architectural Enhancements for Public-Key Cryptography on General-Purpose RISC Processors

VLSI Design

Cite this