Coprozessor für schnellen Speicherabgleich in Multi-DSP Systemen

Calculation speed in multi-processor systems in heavily influenced by communication between the processors. Shared memory and communication links both have their advantages and drawbacks. This project deals with a new idea of placing copies of shared data in every processor and supplying a fast method of updating shared data at certain points during the calculation. This is supported by a specialized processor implemented in field programmable gate arrays /FPGAs) connected to high-speed communication links of a number of signal processors. This results in an increased speedup and a larger number of usable processors and therefore allows the calculation of simulation data in time with natural behavior.