An On-Chip Analog Spectrum Analyzer Based on Miller Frequency Divider

In this work, a novel on-chip spectrum analyzer architecture is proposed based on the principle of Miller regenerative frequency dividers. The integrated spectrum analyzer implementation is challenging due to the high Q on-chip filtering requirement and complex down-conversion architecture. The proposed architecture utilizes a frequency divider for second stage down-conversion without the need for external local oscillator signal, thus resulting in a less complex overall architecture. Moreover, thanks to the proposed architecture, the challenge of down-converting wideband modulated input signal in frequency divider architectures is alleviated. The proposed spectrum analyzer architecture is simulated for three test input signals from 2 GHz to 3 GHz with minimum frequency resolution of 1 MHz, input dynamic range of 40 dB and minimum signal level of 41 dBm. The radio frequency input signal is downconverted to 125 MHz at the analog output of the spectrum analyzer with the good Spurious-free dynamic range (SFDR) of 43 dB.