Modeling State in Software Debugging of VHDL-RTL Designs - A Model-based Diagnosis Approach

Publikation: Beitrag in Buch/Bericht/Konferenzband › Beitrag in einem Konferenzband › Begutachtung

Originalsprache	englisch
Titel	Proceedings of the Fifth International Workshop on Automated Debugging (AADEBUG)
Herausgeber (Verlag)	.
Seiten	197-210
Publikationsstatus	Veröffentlicht - 2003
Veranstaltung	International Workshop on Automated Debugging - Ghent, Belgien Dauer: 8 Sept. 2003 → 10 Sept. 2003

Konferenz	International Workshop on Automated Debugging
Land/Gebiet	Belgien
Ort	Ghent
Zeitraum	8/09/03 → 10/09/03

Andere Dateien und Links

VHDL - Fehlersuche in VHDL-Programmen
Peischl, B. J., Köb, D. & Wotawa, F.
1/11/01 → 31/08/04
Projekt: Forschungsprojekt

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title = "Modeling State in Software Debugging of VHDL-RTL Designs - A Model-based Diagnosis Approach",

author = "Franz Wotawa and Bernhard Peischl",

year = "2003",

language = "English",

pages = "197--210",

booktitle = "Proceedings of the Fifth International Workshop on Automated Debugging (AADEBUG)",

publisher = ".",

note = "International Workshop on Automated Debugging ; Conference date: 08-09-2003 Through 10-09-2003",

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TY - GEN

T1 - Modeling State in Software Debugging of VHDL-RTL Designs - A Model-based Diagnosis Approach

AU - Wotawa, Franz

AU - Peischl, Bernhard

PY - 2003

Y1 - 2003

UR - http://arxiv.org/abs/cs.AI/0311001

M3 - Conference paper

SP - 197

EP - 210

BT - Proceedings of the Fifth International Workshop on Automated Debugging (AADEBUG)

PB - .

T2 - International Workshop on Automated Debugging

Y2 - 8 September 2003 through 10 September 2003

ER -