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Abstract
Modern CPUs dynamically scale voltage and frequency to improve efficiency. Voltages that are too low make the CPU unreliable and, as prior work showed, result in undetected computation errors that can be exploited to compromise systems. Hence, vendors use a generous safety margin at each voltage level, avoiding erroneous computations at the cost of substantial energy overheads.
In this work, we present SUIT, a novel hardware-software co-design to reduce the safety margin substantially without compromising reliability or security. We build on the observation that not all instructions are equally affected by undervolting faults and that most faultable instructions are infre-
quent in practice. Hence, SUIT addresses infrequent faultable instructions via two separate DVFS curves, a conservative and an efficient one. For frequent faultable instructions, SUIT statically relaxes the critical path of the corresponding instructions in hardware. Consequently, the instruction is not faultable anymore on the efficient DVFS curve at the cost of performance overheads for this specific instruction. For infrequent faultable instructions, SUIT introduces a trap mechanism preventing execution on the efficient curve. With this trap mechanism, SUIT temporarily switches to the conservative DVFS curve and switches back if no faultable instruction was executed within a certain time frame. We evaluate all building blocks of SUIT, using both measurements on real hardware and simulations, showing a performance overhead of 3.79 %, and a CPU efficiency gain of 20.8 % on average on SPEC CPU2017.
In this work, we present SUIT, a novel hardware-software co-design to reduce the safety margin substantially without compromising reliability or security. We build on the observation that not all instructions are equally affected by undervolting faults and that most faultable instructions are infre-
quent in practice. Hence, SUIT addresses infrequent faultable instructions via two separate DVFS curves, a conservative and an efficient one. For frequent faultable instructions, SUIT statically relaxes the critical path of the corresponding instructions in hardware. Consequently, the instruction is not faultable anymore on the efficient DVFS curve at the cost of performance overheads for this specific instruction. For infrequent faultable instructions, SUIT introduces a trap mechanism preventing execution on the efficient curve. With this trap mechanism, SUIT temporarily switches to the conservative DVFS curve and switches back if no faultable instruction was executed within a certain time frame. We evaluate all building blocks of SUIT, using both measurements on real hardware and simulations, showing a performance overhead of 3.79 %, and a CPU efficiency gain of 20.8 % on average on SPEC CPU2017.
Originalsprache | englisch |
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Titel | ASPLOS 2024: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1 |
Erscheinungsort | La Jolla, CA, USA |
Herausgeber (Verlag) | Association of Computing Machinery |
ISBN (elektronisch) | 979-8-4007-0385-0/24/04 |
Publikationsstatus | Veröffentlicht - 27 Apr. 2024 |
Veranstaltung | ACM International Conference on Architectural Support for Programming Languages and Operating Systems: ASPLOS 2024 - Hilton La Jolla Torrey Pines, San Diego, USA / Vereinigte Staaten Dauer: 27 Apr. 2024 → 1 Mai 2024 https://www.asplos-conference.org/asplos2024/ |
Konferenz
Konferenz | ACM International Conference on Architectural Support for Programming Languages and Operating Systems |
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Kurztitel | ASPLOS |
Land/Gebiet | USA / Vereinigte Staaten |
Ort | San Diego |
Zeitraum | 27/04/24 → 1/05/24 |
Internetadresse |
Fields of Expertise
- Information, Communication & Computing
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Aktivitäten
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SUIT: Secure Undervolting with Instruction Traps
Juffinger, J. (Redner/in) & Kalinin, S. (Redner/in)
30 Apr. 2024Aktivität: Vortrag oder Präsentation › Vortrag bei Konferenz oder Fachtagung › Science to science
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SUIT: Secure Undervolting with Instruction Traps
Gruss, D. (Redner/in) & Juffinger, J. (Redner/in)
14 Sept. 2024Aktivität: Vortrag oder Präsentation › Invited talk bei Konferenz oder Fachtagung › Science to science
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CPU Undervolting - Exploits and Potentials / SUIT
Juffinger, J. (Redner/in)
22 Jan. 2024Aktivität: Vortrag oder Präsentation › Gastvortrag › Science to science