Architectural Enhancements for Montgomery Multiplication on Embedded RISC Processors

Johann Großschädl, Guy Armand Kamendje

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review

Abstract

Montgomery multiplication normally spends over 90% of its execution time in inner loops executing some kind of multiply-and-add operations. The performance of these critical code sections can be greatly improved by customizing the processor’s instruction set for low-level arithmetic functions. In this paper, we investigate the potential of architectural enhancements for multiple-precision Montgomery multiplication according to the so-called Finely Integrated Product Scanning (FIPS) method. We present instruction set extensions to accelerate the FIPS inner loop operation based on the availability of a multiply/accumulate (MAC) unit with a wide accumulator. Finally, we estimate the execution time of a 1024-bit Montgomery multiplication on an extended MIPS32 core and discuss the impact of the multiplier latency.
Original languageEnglish
Title of host publicationApplied Cryptography and Network Security — ACNS 2003
Place of PublicationBerlin
PublisherSpringer Verlag
Pages418-434
ISBN (Print)3-540-20208-0
DOIs
Publication statusPublished - 2003
Event1st International Conference on Applied Cryptography and Network Security: ACNS 2003 - Kunming, China
Duration: 16 Oct 200319 Oct 2003

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Verlag
Volume2846

Conference

Conference1st International Conference on Applied Cryptography and Network Security
Country/TerritoryChina
CityKunming
Period16/10/0319/10/03

Treatment code (Nähere Zuordnung)

  • Application
  • Experimental

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