Debugging VHDL Designs using Model-Based Reasoning

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	331-351
Journal	Artificial Intelligence in Engineering
Volume	14
Issue number	4
DOIs	https://doi.org/10.1016/S0954-1810(00)00021-2
Publication status	Published - 2000

Treatment code (Nähere Zuordnung)

@article{76f06b9967644249998a32695ae3cfe9,

title = "Debugging VHDL Designs using Model-Based Reasoning",

author = "Franz Wotawa",

year = "2000",

doi = "10.1016/S0954-1810(00)00021-2",

language = "English",

volume = "14",

pages = "331--351",

journal = "Artificial Intelligence in Engineering",

issn = "1879-1492",

publisher = "Elsevier Ltd.",

number = "4",

}