Design Space Exploration of SABER in 65nm ASIC

Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


This paper presents a design space exploration for SABER, one of the finalists in NIST's quantum-resistant public-key cryptographic standardization effort. Our design space exploration targets a 65nm ASIC platform and has resulted in the evaluation of 6 different architectures. Our exploration is initiated by setting a baseline architecture which is ported from FPGA. In order to improve the clock frequency (the primary goal in our exploration), we have employed several optimizations: (i) use of compiled memories in a 'smart synthesis' fashion, (ii) pipelining, and (iii) logic sharing between SABER building blocks. The most optimized architecture utilizes four register files, achieves a remarkable clock frequency of 1GHz while only requiring an area of 0.314mm2. Moreover, physical synthesis is carried out for this architecture and a tapeout-ready layout is presented. The estimated dynamic power consumption of the high-frequency architecture is approximately 184mW for key generation and 187mW for encapsulation or decapsulation operations. These results strongly suggest that our optimized accelerator architecture is well suited for high-speed cryptographic applications.
Original languageEnglish
Title of host publicationASHES '21: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security
Place of PublicationNew York, NY
PublisherAssociation of Computing Machinery
Number of pages6
ISBN (Electronic)978-1-4503-8662-3
Publication statusPublished - Nov 2021
Event5th Workshop on Attacks and Solutions in Hardware Security: ASHES 2021 - Seoul, Hybrider Event, Korea, Republic of
Duration: 19 Nov 2021 → …


Conference5th Workshop on Attacks and Solutions in Hardware Security
Abbreviated titleASHES 2021
Country/TerritoryKorea, Republic of
CityHybrider Event
Period19/11/21 → …

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