Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption

Can Ayduman; Emre Kocer; Selim Kirbiyik; Ahmet Can Mert; Erkay Savaş

doi:10.1109/VLSI-SoC57769.2023.10321943

Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption

Can Ayduman, Emre Kocer, Selim Kirbiyik, Ahmet Can Mert, Erkay Savaş

Institute of Applied Information Processing and Communications (7050)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

This paper presents a design-time configurable hardware generator for hardware acceleration of the CKKS Fully Homomorphic Encryption (FHE) scheme. Our design aims to accelerate the multiplication and relinearization operations of the CKKS. It includes a design-time configurable Number Theoretic Transform (NTT) multiplication hardware for polynomial sizes between 2 ¹⁰ and 2 ¹⁵. The NTT-based multiplication realizes modular multiplication using an efficient word-level Montgomery reduction algorithm.Polynomial multiplication is a bottleneck for the FHE operations. The NTT enables very fast polynomial multiplication by reducing its complexity to O(n_2n) from O(n2). The fundamental arithmetic block of the NTT operation is the butterfly, which implements four different operations, namely, modular multiplication and modular addition/subtraction.The memory access pattern (MAP) of the NTT operation is complex, and it is crucial to design an efficient MAP for NTT for implementing a high-throughput NTT architecture.

Original language	English
Title of host publication	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
Number of pages	7
ISBN (Electronic)	979-8-3503-2599-7
DOIs	https://doi.org/10.1109/VLSI-SoC57769.2023.10321943
Publication status	Published - 22 Nov 2023
Event	31st IFIP/IEEE International Conference on Very Large Scale Integration: VLSI-SoC 2023 - Dubai, United Arab Emirates Duration: 16 Oct 2023 → 18 Oct 2023 Conference number: 31

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	31st IFIP/IEEE International Conference on Very Large Scale Integration
Abbreviated title	VLSI-SoC
Country/Territory	United Arab Emirates
City	Dubai
Period	16/10/23 → 18/10/23

Keywords

acceleration
CKKS
FHE
FPGA
NTT

ASJC Scopus subject areas

Software
Electrical and Electronic Engineering
Hardware and Architecture

Access to Document

10.1109/VLSI-SoC57769.2023.10321943

https://ieeexplore.ieee.org/document/10321943

Cite this

Ayduman, C., Kocer, E., Kirbiyik, S., Mert, A. C., & Savaş, E. (2023). Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption. In 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). https://doi.org/10.1109/VLSI-SoC57769.2023.10321943

Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption. / Ayduman, Can; Kocer, Emre; Kirbiyik, Selim et al.
2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. 2023. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Ayduman, C, Kocer, E, Kirbiyik, S, Mert, AC & Savaş, E 2023, Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption. in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 31st IFIP/IEEE International Conference on Very Large Scale Integration, Dubai, United Arab Emirates, 16/10/23. https://doi.org/10.1109/VLSI-SoC57769.2023.10321943

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title = "Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption",

abstract = "This paper presents a design-time configurable hardware generator for hardware acceleration of the CKKS Fully Homomorphic Encryption (FHE) scheme. Our design aims to accelerate the multiplication and relinearization operations of the CKKS. It includes a design-time configurable Number Theoretic Transform (NTT) multiplication hardware for polynomial sizes between 2 10 and 2 15. The NTT-based multiplication realizes modular multiplication using an efficient word-level Montgomery reduction algorithm.Polynomial multiplication is a bottleneck for the FHE operations. The NTT enables very fast polynomial multiplication by reducing its complexity to O(n_2n) from O(n2). The fundamental arithmetic block of the NTT operation is the butterfly, which implements four different operations, namely, modular multiplication and modular addition/subtraction.The memory access pattern (MAP) of the NTT operation is complex, and it is crucial to design an efficient MAP for NTT for implementing a high-throughput NTT architecture.",

keywords = "acceleration, CKKS, FHE, FPGA, NTT",

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AU - Savaş, Erkay

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N2 - This paper presents a design-time configurable hardware generator for hardware acceleration of the CKKS Fully Homomorphic Encryption (FHE) scheme. Our design aims to accelerate the multiplication and relinearization operations of the CKKS. It includes a design-time configurable Number Theoretic Transform (NTT) multiplication hardware for polynomial sizes between 2 10 and 2 15. The NTT-based multiplication realizes modular multiplication using an efficient word-level Montgomery reduction algorithm.Polynomial multiplication is a bottleneck for the FHE operations. The NTT enables very fast polynomial multiplication by reducing its complexity to O(n_2n) from O(n2). The fundamental arithmetic block of the NTT operation is the butterfly, which implements four different operations, namely, modular multiplication and modular addition/subtraction.The memory access pattern (MAP) of the NTT operation is complex, and it is crucial to design an efficient MAP for NTT for implementing a high-throughput NTT architecture.

AB - This paper presents a design-time configurable hardware generator for hardware acceleration of the CKKS Fully Homomorphic Encryption (FHE) scheme. Our design aims to accelerate the multiplication and relinearization operations of the CKKS. It includes a design-time configurable Number Theoretic Transform (NTT) multiplication hardware for polynomial sizes between 2 10 and 2 15. The NTT-based multiplication realizes modular multiplication using an efficient word-level Montgomery reduction algorithm.Polynomial multiplication is a bottleneck for the FHE operations. The NTT enables very fast polynomial multiplication by reducing its complexity to O(n_2n) from O(n2). The fundamental arithmetic block of the NTT operation is the butterfly, which implements four different operations, namely, modular multiplication and modular addition/subtraction.The memory access pattern (MAP) of the NTT operation is complex, and it is crucial to design an efficient MAP for NTT for implementing a high-throughput NTT architecture.

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Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption

Abstract

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Keywords

ASJC Scopus subject areas

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