Investigating HVDC Converter Stability on AC Faults by Power Hardware in the Loop Method

Manuel Galler, Stefan Christian Polster, Herwig Renner, Robert Schürhuber

Research output: Contribution to conferencePaperpeer-review


In this paper the effects of a sudden vector shift of the terminal voltage on the controller stability of the converter of an embedded VSC-HVDC link are examined. The used model represents an AC transmission corridor with a parallel HVDC-link connecting a stiff grid with a remote grid area. A symmetrical fault on one of the AC lines causes a change in the voltage magnitude and angle at the HVDC terminal. This change is affecting the PLL (Phase Locked Loop) system of the converter controller.
A stable operation of the HVDC converter during the fault and after fault clearing depends on the interaction of its PLL control loop with other implemented control loops, e.g. the current control. The converter controllers work in a rotating reference frame, whereby the PLL provides the actual phase. After a vector shift, the PLL tries to retain a stable operation point to deliver the correct angle information. The time necessary to obtain the new operation point is essential for the stability of the converter controller and thus for the whole HVDC-link control system stability. The control structure investigated consists of classical cascaded converter control structure with an inner current control loop and an outer power control loop.
The simulation results regarding the converter control system are verified in a detailed laboratory measurement with a power hardware in the loop (PHIL) system. The PHIL system consists of a real time simulator in which the grid model, except the HVDC converter control system, is implemented. To get realistic values out of the laboratory measurements, the HVDC converter control is running in a Field Programmable Gate Array (FPGA) which is also used in real converter systems. The FPGA receives the voltage and current information from the point of common coupling (PCC) which is located at the converter bus bar. The analysis of this HVDC link is performed for a specific control scheme with a fixed set of parameters in this fault scenario on an overhead line.
Original languageEnglish
Publication statusPublished - Nov 2021
Event41st CIGRE International Symposium - Ljubljana, Slovenia
Duration: 21 Nov 202124 Nov 2021


Conference41st CIGRE International Symposium


  • HVDC
  • PHIL
  • Converter
  • Vector Shift
  • FPGA

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