Mismatch Reduction Techniques for Current-Mirror Based Potentiostats

Markus Haberler; Inge Siegl; Christoph Steffan; Mario Auer

Mismatch Reduction Techniques for Current-Mirror Based Potentiostats

Markus Haberler^*, Inge Siegl, Christoph Steffan, Mario Auer

^*Corresponding author for this work

Institute of Electronics (4390)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

Current-mirror based potentiostats suffer from systematic and random errors that mainly appear due to mismatch in the current-mirror. To limit the standard deviation of the error to less than 1.1 % over a dynamic range of four decades, either a high overdrive voltage or comparable big transistor dimensions are required. In this work, an optimized design approach for the current-mirror is presented. Based on the given accuracy and dynamic range requirements, an optimized programmable current-mirror is implemented. An accuracy driven design approach is used to achieve the required accuracy over the wide range of sensor currents, while keeping the area consumption low. Compared to a linearly scaled current-mirror based potentiostat design, an output stage area reduction by a factor of four is achieved. Additionally, the voltage headroom consumption is kept at a minimum. The potentiostat is implemented in a 130 nm CMOS technology and consumes an area of only 0.14 mm 2 . The simulation results show that even in the worst case the specified accuracy is achieved over the complete dynamic range of sensor currents from nA to mA.

Original language	English
Title of host publication	2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings
Editors	Marko Koricic, Karolj Skala, Zeljka Car, Marina Cicin-Sain, Vlado Sruk, Dejan Skvorc, Slobodan Ribaric, Bojan Jerbic, Stjepan Gros, Boris Vrdoljak, Mladen Mauher, Edvard Tijan, Tihomir Katulic, Predrag Pale, Tihana Galinac Grbac, Nikola Filip Fijan, Adrian Boukalov, Dragan Cisic, Vera Gradisnik
Publisher	Institute of Electrical and Electronics Engineers
Pages	99-103
Number of pages	5
ISBN (Electronic)	978-953-233-099-1
Publication status	Published - 28 Sept 2020
Event	2020 43rd International Convention on Information, Communication and Electronic Technology: MIPRO 2020 - Opatija, Hybrider Event, Croatia Duration: 28 Sept 2020 → 2 Oct 2020

Conference

Conference	2020 43rd International Convention on Information, Communication and Electronic Technology
Abbreviated title	MIPRO 2020
Country/Territory	Croatia
City	Hybrider Event
Period	28/09/20 → 2/10/20

Keywords

Current-mirror
Dynamic element matching
Point-of-care (PoC) diagnostics
Potentiostat
Wide dynamic range

ASJC Scopus subject areas

Computational Mathematics
Information Systems
Electrical and Electronic Engineering
Hardware and Architecture
Computer Networks and Communications

Access to Document

19_MEET_6235_EC_Version_IEEE_CopyrightAccepted author manuscript, 1.21 MBLicence: CC BY 4.0

Cite this

Haberler, M., Siegl, I., Steffan, C., & Auer, M. (2020). Mismatch Reduction Techniques for Current-Mirror Based Potentiostats. In M. Koricic, K. Skala, Z. Car, M. Cicin-Sain, V. Sruk, D. Skvorc, S. Ribaric, B. Jerbic, S. Gros, B. Vrdoljak, M. Mauher, E. Tijan, T. Katulic, P. Pale, T. G. Grbac, N. F. Fijan, A. Boukalov, D. Cisic, & V. Gradisnik (Eds.), 2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings (pp. 99-103). Article 9245441 Institute of Electrical and Electronics Engineers.

Mismatch Reduction Techniques for Current-Mirror Based Potentiostats. / Haberler, Markus; Siegl, Inge; Steffan, Christoph et al.
2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings. ed. / Marko Koricic; Karolj Skala; Zeljka Car; Marina Cicin-Sain; Vlado Sruk; Dejan Skvorc; Slobodan Ribaric; Bojan Jerbic; Stjepan Gros; Boris Vrdoljak; Mladen Mauher; Edvard Tijan; Tihomir Katulic; Predrag Pale; Tihana Galinac Grbac; Nikola Filip Fijan; Adrian Boukalov; Dragan Cisic; Vera Gradisnik. Institute of Electrical and Electronics Engineers, 2020. p. 99-103 9245441.

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Haberler, M, Siegl, I, Steffan, C & Auer, M 2020, Mismatch Reduction Techniques for Current-Mirror Based Potentiostats. in M Koricic, K Skala, Z Car, M Cicin-Sain, V Sruk, D Skvorc, S Ribaric, B Jerbic, S Gros, B Vrdoljak, M Mauher, E Tijan, T Katulic, P Pale, TG Grbac, NF Fijan, A Boukalov, D Cisic & V Gradisnik (eds), 2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings., 9245441, Institute of Electrical and Electronics Engineers, pp. 99-103, 2020 43rd International Convention on Information, Communication and Electronic Technology, Hybrider Event, Croatia, 28/09/20.

Haberler M, Siegl I, Steffan C, Auer M. Mismatch Reduction Techniques for Current-Mirror Based Potentiostats. In Koricic M, Skala K, Car Z, Cicin-Sain M, Sruk V, Skvorc D, Ribaric S, Jerbic B, Gros S, Vrdoljak B, Mauher M, Tijan E, Katulic T, Pale P, Grbac TG, Fijan NF, Boukalov A, Cisic D, Gradisnik V, editors, 2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings. Institute of Electrical and Electronics Engineers. 2020. p. 99-103. 9245441

Haberler, Markus ; Siegl, Inge ; Steffan, Christoph et al. / Mismatch Reduction Techniques for Current-Mirror Based Potentiostats. 2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings. editor / Marko Koricic ; Karolj Skala ; Zeljka Car ; Marina Cicin-Sain ; Vlado Sruk ; Dejan Skvorc ; Slobodan Ribaric ; Bojan Jerbic ; Stjepan Gros ; Boris Vrdoljak ; Mladen Mauher ; Edvard Tijan ; Tihomir Katulic ; Predrag Pale ; Tihana Galinac Grbac ; Nikola Filip Fijan ; Adrian Boukalov ; Dragan Cisic ; Vera Gradisnik. Institute of Electrical and Electronics Engineers, 2020. pp. 99-103

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AB - Current-mirror based potentiostats suffer from systematic and random errors that mainly appear due to mismatch in the current-mirror. To limit the standard deviation of the error to less than 1.1 % over a dynamic range of four decades, either a high overdrive voltage or comparable big transistor dimensions are required. In this work, an optimized design approach for the current-mirror is presented. Based on the given accuracy and dynamic range requirements, an optimized programmable current-mirror is implemented. An accuracy driven design approach is used to achieve the required accuracy over the wide range of sensor currents, while keeping the area consumption low. Compared to a linearly scaled current-mirror based potentiostat design, an output stage area reduction by a factor of four is achieved. Additionally, the voltage headroom consumption is kept at a minimum. The potentiostat is implemented in a 130 nm CMOS technology and consumes an area of only 0.14 mm 2 . The simulation results show that even in the worst case the specified accuracy is achieved over the complete dynamic range of sensor currents from nA to mA.

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Mismatch Reduction Techniques for Current-Mirror Based Potentiostats

Abstract

Conference

Keywords

ASJC Scopus subject areas

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