Reducing the communication bottleneck via on-chip cosimulation of gate-level hdl and c-models on a hardware accelerator

Alexander Maili, Christian Steger, Reinhold Weiß, Rob Quigley, Damian Dalton

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Original language	English
Title of host publication	New frontiers in VLSI design
Place of Publication	Los Alamitos, Calif.
Publisher	IEEE Computer Soc.
ISBN (Print)	0-7695-2365-X
Publication status	Submitted - 2005
Event	IEEE Computer Society Annual Symposium on VLSI - Tampa / Florida, United States Duration: 11 May 2005 → 12 May 2005

Conference	IEEE Computer Society Annual Symposium on VLSI
Country/Territory	United States
City	Tampa / Florida
Period	11/05/05 → 12/05/05

Hardware/Software-Codesign
Steger, C., Seifert, C., Stelzer, P., Feldbacher, M., Fiala, G. & Basic, F.
1/01/95 → …
Project: Research area

Cite this

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title = "Reducing the communication bottleneck via on-chip cosimulation of gate-level hdl and c-models on a hardware accelerator",

author = "Alexander Maili and Christian Steger and Reinhold Wei{\ss} and Rob Quigley and Damian Dalton",

note = ", Seite von - bis: -; IEEE Computer Society Annual Symposium on VLSI ; Conference date: 11-05-2005 Through 12-05-2005",

year = "2005",

language = "English",

isbn = "0-7695-2365-X",

booktitle = "New frontiers in VLSI design",

publisher = "IEEE Computer Soc.",

}

TY - GEN

T1 - Reducing the communication bottleneck via on-chip cosimulation of gate-level hdl and c-models on a hardware accelerator

AU - Maili, Alexander

AU - Steger, Christian

AU - Weiß, Reinhold

AU - Quigley, Rob

AU - Dalton, Damian

N1 - , Seite von - bis: -

PY - 2005

Y1 - 2005

M3 - Conference paper

SN - 0-7695-2365-X

BT - New frontiers in VLSI design

PB - IEEE Computer Soc.

CY - Los Alamitos, Calif.

T2 - IEEE Computer Society Annual Symposium on VLSI

Y2 - 11 May 2005 through 12 May 2005

ER -