Reducing the communication bottleneck via on-chip cosimulation of gate-level hdl and c-models on a hardware accelerator

Alexander Maili, Christian Steger, Reinhold Weiß, Rob Quigley, Damian Dalton

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review

Original languageEnglish
Title of host publicationNew frontiers in VLSI design
Place of PublicationLos Alamitos, Calif.
PublisherIEEE Computer Soc.
ISBN (Print)0-7695-2365-X
Publication statusSubmitted - 2005
EventIEEE Computer Society Annual Symposium on VLSI - Tampa / Florida, United States
Duration: 11 May 200512 May 2005


ConferenceIEEE Computer Society Annual Symposium on VLSI
Country/TerritoryUnited States
CityTampa / Florida

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