Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard

Guangyao Shen; Victor Khilkevich; Sen Yang; David Pommerenke; Hermann Aichele; Dirk Eichel; Christoph Keller

doi:10.1109/ISEMC.2014.6899015

Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard

Guangyao Shen, Victor Khilkevich, Sen Yang, David Pommerenke, Hermann Aichele, Dirk Eichel, Christoph Keller

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

Original language	English
Title of host publication	2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)
Pages	455-459
Number of pages	5
DOIs	https://doi.org/10.1109/ISEMC.2014.6899015
Publication status	Published - 15 Sept 2014
Externally published	Yes
Event	2014 IEEE International Symposium on Electromagnetic Compatibility: EMC 2014 - Raleigh, United States Duration: 3 Aug 2014 → 8 Aug 2014

Conference

Conference	2014 IEEE International Symposium on Electromagnetic Compatibility
Country/Territory	United States
City	Raleigh
Period	3/08/14 → 8/08/14

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/ISEMC.2014.6899015

Cite this

Shen, G, Khilkevich, V, Yang, S, Pommerenke, D, Aichele, H, Eichel, D & Keller, C 2014, Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard. in 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC). pp. 455-459, 2014 IEEE International Symposium on Electromagnetic Compatibility, Raleigh, United States, 3/08/14. https://doi.org/10.1109/ISEMC.2014.6899015

@inproceedings{007c588e4472414baf8ce05afa293bf7,

title = "Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard",

abstract = "As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.",

author = "Guangyao Shen and Victor Khilkevich and Sen Yang and David Pommerenke and Hermann Aichele and Dirk Eichel and Christoph Keller",

year = "2014",

month = sep,

day = "15",

doi = "10.1109/ISEMC.2014.6899015",

language = "English",

isbn = "978-1-4799-5544-2",

pages = "455--459",

booktitle = "2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)",

note = "2014 IEEE International Symposium on Electromagnetic Compatibility : EMC 2014 ; Conference date: 03-08-2014 Through 08-08-2014",

}

TY - GEN

T1 - Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard

AU - Shen, Guangyao

AU - Khilkevich, Victor

AU - Yang, Sen

AU - Pommerenke, David

AU - Aichele, Hermann

AU - Eichel, Dirk

AU - Keller, Christoph

PY - 2014/9/15

Y1 - 2014/9/15

N2 - As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

AB - As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

UR - http://www.scopus.com/inward/record.url?scp=84931837670&partnerID=8YFLogxK

U2 - 10.1109/ISEMC.2014.6899015

DO - 10.1109/ISEMC.2014.6899015

M3 - Conference paper

AN - SCOPUS:84931837670

SN - 978-1-4799-5544-2

SP - 455

EP - 459

BT - 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)

T2 - 2014 IEEE International Symposium on Electromagnetic Compatibility

Y2 - 3 August 2014 through 8 August 2014

ER -

Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard

Abstract

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Cite this