TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state

Benjamin Orr; Krzysztof Domanski; Harald Gossner; David Pommerenke

doi:10.1109/EOSESD.2016.7592566

TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state

Benjamin Orr, Krzysztof Domanski, Harald Gossner, David Pommerenke

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

In this paper, the interaction between the ESD protection concept and a powered output driver in a 40 nm CMOS process are investigated and characterized by TLP. By using IO test chips designed for HBM and CDM validation, the IV behavior of the pin is measured with the driver placed into various states.

Original language	English
Title of host publication	Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016
Publisher	ESD Association
ISBN (Electronic)	9781585372898
DOIs	https://doi.org/10.1109/EOSESD.2016.7592566
Publication status	Published - 14 Oct 2016
Externally published	Yes
Event	38th Annual Electrical Overstress/Electrostatic Discharge Symposium: EOS/ESD 2016 - Garden Grove (Anaheim), United States Duration: 11 Sept 2016 → 16 Sept 2016

Publication series

Name	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume	2016-October
ISSN (Print)	0739-5159

Conference

Conference	38th Annual Electrical Overstress/Electrostatic Discharge Symposium
Country/Territory	United States
City	Garden Grove (Anaheim)
Period	11/09/16 → 16/09/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EOSESD.2016.7592566

Cite this

Orr, B., Domanski, K., Gossner, H., & Pommerenke, D. (2016). TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016 Article 7592566 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Vol. 2016-October). ESD Association. https://doi.org/10.1109/EOSESD.2016.7592566

TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state. / Orr, Benjamin; Domanski, Krzysztof; Gossner, Harald et al.
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016. ESD Association, 2016. 7592566 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Vol. 2016-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Orr, B, Domanski, K, Gossner, H & Pommerenke, D 2016, TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state. in Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016., 7592566, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, vol. 2016-October, ESD Association, 38th Annual Electrical Overstress/Electrostatic Discharge Symposium, Garden Grove (Anaheim), United States, 11/09/16. https://doi.org/10.1109/EOSESD.2016.7592566

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TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state

Abstract

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Conference

ASJC Scopus subject areas

Access to Document

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