Suit up! Made-to-Measure Hardware Implementations of ASCON

Hannes Groß; Erich Wenger; Christoph Erwin Dobraunig; Christoph Ehrenhöfer

doi:10.1109/DSD.2015.14

Suit up! Made-to-Measure Hardware Implementations of ASCON

Hannes Groß, Erich Wenger, Christoph Erwin Dobraunig, Christoph Ehrenhöfer

Institute of Applied Information Processing and Communications (7050)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

Having ciphers that provide confidentiality and authenticity, that are fast in software and efficient in hardware, these are the goals of the CAESAR authenticated encryption competition. In this paper, the promising CAESAR candidate ASCON is implemented in hardware and optimized for different typical applications to fully explore ASCON's design space. Thus, we are able to present hardware implementations of Ascon suitable for RFID tags, Wireless Sensor Nodes, Embedded Systems, and applications that need maximum performance. For instance, we show that an ASCON implementation with a single unrolled round transformation is only 7 kGE large, but can process up to 5.5 Gbit/sec of data (0.75 cycles/byte), which is already enough to encrypt a Gigabit Ethernet connection. Besides, ASCON is not only fast and small, it can also be easily protected against DPA attacks. A threshold implementation of ASCON just requires about 8 kGE of chip area, which is only 3.1 times larger than the unprotected low-area optimized implementation.

Original language	English
Title of host publication	18th Euromicro Conference on Digital Systems Design
Place of Publication	Los Alamitos
Publisher	IEEE Computer Society
Pages	645-652
DOIs	https://doi.org/10.1109/DSD.2015.14
Publication status	Published - 2015
Event	18th Euromicro Conference on Digital Systems Design - Funchal, Madeira, Portugal Duration: 26 Aug 2015 → 28 Aug 2015

Conference

Conference	18th Euromicro Conference on Digital Systems Design
Country/Territory	Portugal
City	Funchal, Madeira
Period	26/08/15 → 28/08/15

Fields of Expertise

Information, Communication & Computing

Access to Document

10.1109/DSD.2015.14

2015_ascon_hardware_ieee.pdfAccepted author manuscript, 399 KB

SeCoS - Secure Contactless Sphere - Smart RFID-Technologies for a Connected World
Bösch, W., Wenger, E., Khan, H. N., Schmidt, J., Gadringer, M. E., Spreitzer, R. C., Mendel, F., Gruss, D., Hutter, M., Freidl, P. F., Görtschacher, L. J., Mangard, S. & Grosinger, J.
1/01/13 → 31/12/15
Project: Research project
RFID Security
Wenger, E., Hutter, M., Oswald, M. E., Posch, K., Plos, T., Herbst, C., Schmidt, J., Feldhofer, M., Szekely, A., Dominikus, S., Aigner, M. J., Kirschbaum, M., Medwed, M. & Posch, R.
1/01/05 → 15/07/19
Project: Research area
VLSI Design
Medwed, M., Wenger, E., Aigner, M. J., Posch, K., Hutter, M., Kirschbaum, M., Schmidt, J., Posch, R., Dominikus, S., Szekely, A., Feldhofer, M. & Plos, T.
1/01/95 → 15/07/19
Project: Research area

Cite this

@inproceedings{8c4e7b87747f4eb89d114bf2e1f1614f,

title = "Suit up! Made-to-Measure Hardware Implementations of ASCON",

abstract = "Having ciphers that provide confidentiality and authenticity, that are fast in software and efficient in hardware, these are the goals of the CAESAR authenticated encryption competition. In this paper, the promising CAESAR candidate ASCON is implemented in hardware and optimized for different typical applications to fully explore ASCON's design space. Thus, we are able to present hardware implementations of Ascon suitable for RFID tags, Wireless Sensor Nodes, Embedded Systems, and applications that need maximum performance. For instance, we show that an ASCON implementation with a single unrolled round transformation is only 7 kGE large, but can process up to 5.5 Gbit/sec of data (0.75 cycles/byte), which is already enough to encrypt a Gigabit Ethernet connection. Besides, ASCON is not only fast and small, it can also be easily protected against DPA attacks. A threshold implementation of ASCON just requires about 8 kGE of chip area, which is only 3.1 times larger than the unprotected low-area optimized implementation.",

author = "Hannes Gro{\ss} and Erich Wenger and Dobraunig, {Christoph Erwin} and Christoph Ehrenh{\"o}fer",

year = "2015",

doi = "10.1109/DSD.2015.14",

language = "English",

pages = "645--652",

booktitle = "18th Euromicro Conference on Digital Systems Design",

publisher = "IEEE Computer Society",

address = "United States",

note = "18th Euromicro Conference on Digital Systems Design ; Conference date: 26-08-2015 Through 28-08-2015",

}

TY - GEN

T1 - Suit up! Made-to-Measure Hardware Implementations of ASCON

AU - Groß, Hannes

AU - Wenger, Erich

AU - Dobraunig, Christoph Erwin

AU - Ehrenhöfer, Christoph

PY - 2015

Y1 - 2015

N2 - Having ciphers that provide confidentiality and authenticity, that are fast in software and efficient in hardware, these are the goals of the CAESAR authenticated encryption competition. In this paper, the promising CAESAR candidate ASCON is implemented in hardware and optimized for different typical applications to fully explore ASCON's design space. Thus, we are able to present hardware implementations of Ascon suitable for RFID tags, Wireless Sensor Nodes, Embedded Systems, and applications that need maximum performance. For instance, we show that an ASCON implementation with a single unrolled round transformation is only 7 kGE large, but can process up to 5.5 Gbit/sec of data (0.75 cycles/byte), which is already enough to encrypt a Gigabit Ethernet connection. Besides, ASCON is not only fast and small, it can also be easily protected against DPA attacks. A threshold implementation of ASCON just requires about 8 kGE of chip area, which is only 3.1 times larger than the unprotected low-area optimized implementation.

AB - Having ciphers that provide confidentiality and authenticity, that are fast in software and efficient in hardware, these are the goals of the CAESAR authenticated encryption competition. In this paper, the promising CAESAR candidate ASCON is implemented in hardware and optimized for different typical applications to fully explore ASCON's design space. Thus, we are able to present hardware implementations of Ascon suitable for RFID tags, Wireless Sensor Nodes, Embedded Systems, and applications that need maximum performance. For instance, we show that an ASCON implementation with a single unrolled round transformation is only 7 kGE large, but can process up to 5.5 Gbit/sec of data (0.75 cycles/byte), which is already enough to encrypt a Gigabit Ethernet connection. Besides, ASCON is not only fast and small, it can also be easily protected against DPA attacks. A threshold implementation of ASCON just requires about 8 kGE of chip area, which is only 3.1 times larger than the unprotected low-area optimized implementation.

U2 - 10.1109/DSD.2015.14

DO - 10.1109/DSD.2015.14

M3 - Conference paper

SP - 645

EP - 652

BT - 18th Euromicro Conference on Digital Systems Design

PB - IEEE Computer Society

CY - Los Alamitos

T2 - 18th Euromicro Conference on Digital Systems Design

Y2 - 26 August 2015 through 28 August 2015

ER -

Suit up! Made-to-Measure Hardware Implementations of ASCON

Abstract

Conference

Fields of Expertise

Access to Document

Fingerprint

Projects

SeCoS - Secure Contactless Sphere - Smart RFID-Technologies for a Connected World

RFID Security

VLSI Design

Cite this