Hardware/software co-designed security extensions for embedded devices

Maja Malenko*, Marcel Baunach

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


The rise of the Internet of Things (IoT) has dramatically increased the number of low-cost embedded devices. Being introduced into today’s connected cyber-physical world, these devices now become vulnerable, especially if they offer no protection mechanisms. In this work we present a hardware/software co-designed memory protection approach that provides efficient, cheap, and effective isolation of tasks. The security extensions are implemented into a RISC-V-based MCU and a microkernel-based operating system. Our FPGA prototype shows that the hardware extensions use less than 5.5% of its area in terms of LUTs, and 24.7% in terms of FFs. They impose an extra 28% of context switch time, while providing protection of shared on-chip peripherals and authenticated communication via shared memory.

Original languageEnglish
Title of host publicationArchitecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings
EditorsThilo Pionteck, Jürgen Brehm, Sascha Uhrig, Christian Hochberger, Martin Schoeberl
PublisherSpringer-Verlag Italia
Number of pages12
ISBN (Print)9783030186555
Publication statusPublished - 1 Jan 2019
Event32nd International Conference on Architecture of Computing Systems, ARCS 2019 - Copenhagen, Denmark
Duration: 20 May 201923 May 2019

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume11479 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference32nd International Conference on Architecture of Computing Systems, ARCS 2019


  • Inter-task communication
  • Memory protection
  • MPU
  • Resource protection
  • RISC-V

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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