Hardware/software co-designed security extensions for embedded devices

Maja Malenko; Marcel Baunach

doi:10.1007/978-3-030-18656-2_1

Hardware/software co-designed security extensions for embedded devices

Maja Malenko^*, Marcel Baunach

^*Corresponding author for this work

Institute of Technical Informatics (4480)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

The rise of the Internet of Things (IoT) has dramatically increased the number of low-cost embedded devices. Being introduced into today’s connected cyber-physical world, these devices now become vulnerable, especially if they offer no protection mechanisms. In this work we present a hardware/software co-designed memory protection approach that provides efficient, cheap, and effective isolation of tasks. The security extensions are implemented into a RISC-V-based MCU and a microkernel-based operating system. Our FPGA prototype shows that the hardware extensions use less than 5.5% of its area in terms of LUTs, and 24.7% in terms of FFs. They impose an extra 28% of context switch time, while providing protection of shared on-chip peripherals and authenticated communication via shared memory.

Original language	English
Title of host publication	Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings
Editors	Thilo Pionteck, Jürgen Brehm, Sascha Uhrig, Christian Hochberger, Martin Schoeberl
Publisher	Springer-Verlag Italia
Pages	3-14
Number of pages	12
ISBN (Print)	9783030186555
DOIs	https://doi.org/10.1007/978-3-030-18656-2_1
Publication status	Published - 1 Jan 2019
Event	32nd International Conference on Architecture of Computing Systems, ARCS 2019 - Copenhagen, Denmark Duration: 20 May 2019 → 23 May 2019

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	11479 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	32nd International Conference on Architecture of Computing Systems, ARCS 2019
Country/Territory	Denmark
City	Copenhagen
Period	20/05/19 → 23/05/19

Keywords

Inter-task communication
Memory protection
MPU
Resource protection
RISC-V

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-030-18656-2_1

Cite this

Malenko, M., & Baunach, M. (2019). Hardware/software co-designed security extensions for embedded devices. In T. Pionteck, J. Brehm, S. Uhrig, C. Hochberger, & M. Schoeberl (Eds.), Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings (pp. 3-14). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 11479 LNCS). Springer-Verlag Italia. https://doi.org/10.1007/978-3-030-18656-2_1

Hardware/software co-designed security extensions for embedded devices. / Malenko, Maja; Baunach, Marcel.

Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings. ed. / Thilo Pionteck; Jürgen Brehm; Sascha Uhrig; Christian Hochberger; Martin Schoeberl. Springer-Verlag Italia, 2019. p. 3-14 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 11479 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Malenko, M & Baunach, M 2019, Hardware/software co-designed security extensions for embedded devices. in T Pionteck, J Brehm, S Uhrig, C Hochberger & M Schoeberl (eds), Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 11479 LNCS, Springer-Verlag Italia, pp. 3-14, 32nd International Conference on Architecture of Computing Systems, ARCS 2019, Copenhagen, Denmark, 20/05/19. https://doi.org/10.1007/978-3-030-18656-2_1

Malenko M, Baunach M. Hardware/software co-designed security extensions for embedded devices. In Pionteck T, Brehm J, Uhrig S, Hochberger C, Schoeberl M, editors, Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings. Springer-Verlag Italia. 2019. p. 3-14. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-030-18656-2_1

Malenko, Maja ; Baunach, Marcel. / Hardware/software co-designed security extensions for embedded devices. Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings. editor / Thilo Pionteck ; Jürgen Brehm ; Sascha Uhrig ; Christian Hochberger ; Martin Schoeberl. Springer-Verlag Italia, 2019. pp. 3-14 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{cccc5468ffa143a49b9644c7980757d5,

title = "Hardware/software co-designed security extensions for embedded devices",

abstract = "The rise of the Internet of Things (IoT) has dramatically increased the number of low-cost embedded devices. Being introduced into today{\textquoteright}s connected cyber-physical world, these devices now become vulnerable, especially if they offer no protection mechanisms. In this work we present a hardware/software co-designed memory protection approach that provides efficient, cheap, and effective isolation of tasks. The security extensions are implemented into a RISC-V-based MCU and a microkernel-based operating system. Our FPGA prototype shows that the hardware extensions use less than 5.5% of its area in terms of LUTs, and 24.7% in terms of FFs. They impose an extra 28% of context switch time, while providing protection of shared on-chip peripherals and authenticated communication via shared memory.",

keywords = "Inter-task communication, Memory protection, MPU, Resource protection, RISC-V",

author = "Maja Malenko and Marcel Baunach",

year = "2019",

month = jan,

day = "1",

doi = "10.1007/978-3-030-18656-2_1",

language = "English",

isbn = "9783030186555",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer-Verlag Italia",

pages = "3--14",

editor = "Thilo Pionteck and J{\"u}rgen Brehm and Sascha Uhrig and Christian Hochberger and Martin Schoeberl",

booktitle = "Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings",

address = "Italy",

note = "32nd International Conference on Architecture of Computing Systems, ARCS 2019 ; Conference date: 20-05-2019 Through 23-05-2019",

}

TY - GEN

T1 - Hardware/software co-designed security extensions for embedded devices

AU - Malenko, Maja

AU - Baunach, Marcel

PY - 2019/1/1

Y1 - 2019/1/1

N2 - The rise of the Internet of Things (IoT) has dramatically increased the number of low-cost embedded devices. Being introduced into today’s connected cyber-physical world, these devices now become vulnerable, especially if they offer no protection mechanisms. In this work we present a hardware/software co-designed memory protection approach that provides efficient, cheap, and effective isolation of tasks. The security extensions are implemented into a RISC-V-based MCU and a microkernel-based operating system. Our FPGA prototype shows that the hardware extensions use less than 5.5% of its area in terms of LUTs, and 24.7% in terms of FFs. They impose an extra 28% of context switch time, while providing protection of shared on-chip peripherals and authenticated communication via shared memory.

AB - The rise of the Internet of Things (IoT) has dramatically increased the number of low-cost embedded devices. Being introduced into today’s connected cyber-physical world, these devices now become vulnerable, especially if they offer no protection mechanisms. In this work we present a hardware/software co-designed memory protection approach that provides efficient, cheap, and effective isolation of tasks. The security extensions are implemented into a RISC-V-based MCU and a microkernel-based operating system. Our FPGA prototype shows that the hardware extensions use less than 5.5% of its area in terms of LUTs, and 24.7% in terms of FFs. They impose an extra 28% of context switch time, while providing protection of shared on-chip peripherals and authenticated communication via shared memory.

KW - Inter-task communication

KW - Memory protection

KW - MPU

KW - Resource protection

KW - RISC-V

UR - http://www.scopus.com/inward/record.url?scp=85065865783&partnerID=8YFLogxK

U2 - 10.1007/978-3-030-18656-2_1

DO - 10.1007/978-3-030-18656-2_1

M3 - Conference paper

AN - SCOPUS:85065865783

SN - 9783030186555

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 3

EP - 14

BT - Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Proceedings

A2 - Pionteck, Thilo

A2 - Brehm, Jürgen

A2 - Uhrig, Sascha

A2 - Hochberger, Christian

A2 - Schoeberl, Martin

PB - Springer-Verlag Italia

T2 - 32nd International Conference on Architecture of Computing Systems, ARCS 2019

Y2 - 20 May 2019 through 23 May 2019

ER -

Hardware/software co-designed security extensions for embedded devices

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Embedded Operating Systems

Embedded Automotive Systems

Reconfigurable Processor Architectures

Cite this

Hardware/software co-designed security extensions for embedded devices

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Projects

Embedded Operating Systems

Embedded Automotive Systems

Reconfigurable Processor Architectures

Cite this